Creating a 'coral reef' of heat sinks to cool high-powered Intel chips
“Our research shows how boiling is an effective and efficient means of cooling, especially for the high-power chips used for AI applications,” said Justin A. Weibel, professor of mechanical engineering and director of the Cooling Technologies Research Center (CTRC) at Purdue. “Now we are working with Intel to take a giant leap forward with a topologically optimized 3D heat sink designed specifically for two-phase immersion cooling.”
This three-year, $1.71 million award for Intel (in collaboration with Purdue) comes from ARPA-E, the Advanced Research Projects Agency of the Department of Energy.
In two-phase immersion cooling, the semiconductor itself is immersed in a dielectric liquid. The chip’s heat boils the liquid, and the bubbles carry away the heat. But the magic comes in the heat sink attached to the chip.
“The breakthrough here is using topology optimization to design a heat sink for immersion cooling,” Weibel said. “If we attached a standard heat sink to a high-power immersion cooled chip, bubbles wouldn’t even form on most of the surfaces. We have to go through a new design process that shapes the surface based on models of the boiling process.”
In topology optimization, a computer simulation iterates thousands of versions of a design, changing it slightly each time to compare which results are better. By the end of the process, the “ideal” shape turned out to resemble corals.
“This is poetic if you look at nature,” Weibel said. “Corals live their life underwater, and their shape came about for a reason. So when we tasked the algorithm to design a heat sink to function while immersed in liquid, it is befitting that the resulting shape imitates this biology.”
Another element of the design is a boiling enhancement coating to be applied on the heat sinks, to be fabricated by the other collaborator on the award, Advanced Cooling Technologies. This fine-particle coating is designed to create even more tiny nucleation sites on the shape, enabling even more bubbles to form.
“The other great thing about this approach is that we can design for compactness to pack multiple heat sinks close together,” Weibel said. “Lining up many in a row, just like real chips would be in a datacenter, this 'coral reef' of copper heat sinks can enable entirely passive cooling of these high-performance chips, maximizing the overall energy efficiency of the system.”
Representatives from Intel recently visited Purdue to tour the Birck Nanotechnology Center, as well as the Rosen Center for Advanced Computing. “They were blown away by what we had here,” Weibel said. “My students have already created the testbed to combine their chips and our heat sinks. It was a very positive visit. Everyone is looking forward to running the experiments and seeing the results.”
The project is part of ARPA-E’s COOLERCHIPS initiative, aimed at creating more efficient data centers. It is one of several COOLERCHIPS initiatives Purdue University researchers are involved in. It also aligns with Purdue Computes, a university-wide initiative emphasizing computing, data science, semiconductors, and physical implementations of artificial intelligence.
“Our overall goal is to reduce energy consumed by these datacenters,” Weibel said. “If we can do that with just the physical shape of a heat sink, that eliminates the need for big pumps, fans, and other components. Scale that up to multiple datacenters, and the energy and operational costs savings would be huge.”
Source: Justin Weibel, jaweibel@purdue.edu
Writer: Jared Pike, jaredpike@purdue.edu, 765-496-0374