Wei will receive a one-time award of $50,000 to support his research or curriculum development, enhance computer lab infrastructure at Purdue University, and gain networking opportunities with Intel technical leaders, including presentations at Intel-sponsored events.

"I'm honored to receive this fantastic award and excited for the opportunities to facilitate long-term collaborative relationships with senior technical leaders at Intel in the area of semiconductor packaging," said Wei. "I deeply appreciate the advice, support, and research contributions from my mentors, collaborators, and students. Semiconductors are a vital part of our economy and society, and I'm excited to be involved at the forefront of semiconductor research here at Purdue."

Tiwei Wei’s research focuses on solving the fabrication challenges and heat transfer issues in advanced semiconductor packaging and assembly. He is developing new materials and techniques for scaling 3D interconnect density, including through silicon vias (TSVs), through glass vias (TGVs), Cu/Sn microbump bonding, and Cu/SiO2 hybrid bonding. In addition, his lab is investigating the fundamental thermal, mechanical, and electrical behaviors associated with these scaling 3D metal interconnects. With support from the Semiconductor Research Corporation (SRC), he and his collaborator Thomas Beechem reported the resulting stresses via Raman spectroscopy for in-house developed blind TSVs with diameters as small as 1 μm. Moreover, his team has explored integrating micro/nanoscale porous copper inverse opals (CIO) structure into fine-pitch Sn-based solder microbumps to enhance the thermal conductivity and mechanical reliability in 3D semiconductor devices. This development targets achieving ultra-high 3D interconnect densities ranging from 1E+6/mm2 to 1E+8/mm2 for next-generation 3D integration systems, including applications such as memory-on-logic stacking, High Bandwidth Memory (HBM), and backside power delivery networks (BS-PDN).

Wei also introduced hotspot targeted microjet cooling to address potential temperature non-uniformity from different functional blocks within processors. Additionally, Wei led a team to raise $1.8 million funding from DOE ARPA-E COOLERCHIPS program to develop a chip/package level confined two-phase microjet cooling, which utilizes porous structure surface enhancement and phase separations. These innovative solutions are expected to pave the way for more efficient thermal management in high-density advanced packaging and 3D integration. The goal of this program is to develop an advanced heat transfer and packaging concept and rapidly evolving it to a system solution that can yield great energy savings for the data center at cooling energy less than 5% IT load. It aims to achieve this while maintaining reliability at similar levels to air-cooling at any time and any U.S. location for future high-density (AI/kW) chipsets and servers at approximately 3 kW/U. COOLERCHIPS aims to be commercially competitive with current state-of-the-art solutions by offering a lower total cost of ownership without compromising data center reliability and availability.

Wei is a highly engaged and enthusiastic educator who actively seeks to promote student engagement in the classroom. Since joining Purdue University as an assistant professor in July 2022, he has taught courses such as ME 315 Heat and Mass Transfer, ME 505 Intermediate Heat Transfer, and the newly developed course ME/ECE 595 "Reliability Physics of Advanced Packaging. Dr. Wei has made significant contributions to mentoring the semiconductor workforce at Purdue, guiding over 15 undergraduate students, including 8 participants in the SCALE semiconductor packaging program. Under his mentorship, three SCALE students have earned prestigious awards, including the Best SCALE Poster Presentation Award and the Best Poster Presentation Award (out of 300) at the SURF event at Purdue.

In addition to teaching and research, Wei is also organizing the Symposium on Reliability for Electronics and Photonics Packaging (REPP), to be hosted at Purdue University in November 2024.

His work takes place at Birck Nanotechnology Center, which recently hosted a visit from NSF Director Sethuraman Panchanathan and U.S. Senator Todd Young to inaugurate $100 million of upgrades focusing solely on semiconductor research. It's part of the Purdue Computes initiative, focusing on the persistent pursuit of semiconductor excellence. In 2020, the University launched the nation’s first comprehensive degree program in semiconductors. In April 2024, South Korean company SK hynix Inc. announced plans to build a nearly $4 billion advanced packaging fabrication and R&D facility in the Purdue Research Park.