2023 Research Projects
Projects are posted below; new projects will continue to be posted. To learn more about the type of research conducted by undergraduates, view the archived symposium booklets and search the past SURF projects.
This is a list of research projects that may have opportunities for undergraduate students. Please note that it is not a complete list of every SURF project. Undergraduates will discover other projects when talking directly to Purdue faculty.
You can browse all the projects on the list or view only projects in the following categories:
Computer Architecture (3)
Multi-rotor Trajectory Planning
Description:
This project will focus on development of a multi-rotor 3D trajectory planner using the Casadi library and deployment on an open source autopilot. Path-planning in cluttered environments is a challenging task, and this project intends to make the algorithms more accessible to students and researchers in general.
One of the most significant hurdles in training students in the field of robotics, is the difficulty of embedded development. The Casadi library builds an equation graph that is quite similar to tensor flow used in machine learning. This equation graph can be used to compute gradients and jacobians using automatic differentiation across the graph which makes it an excellent candidate for use in optimal control and trajectory generation.
Another benefit of the Casadi library is that the equation graph can be used to generate efficient C-code that implements the algorithms for deployment to hardware systems. The Casadi library is built using C++ but the interfaces to Python and code generation to C make it quite flexible. Equations can be concisely represented in the Casadi language using the python language, that students can readily understand and modify.
The project will be conducted at the Purdue UAS Research and Test (PURT) facility. PURT is the largest indoor motion capture facility in the world. It is housed in an aircraft hangar at the Purdue airport and consists of 60 Qualisys Oqus7+ motion capture cameras. These cameras can track rigid bodies moving in the facility with 1 mm accuracy. In developing trajectory tracking algorithms, the students will be leveraging state of the art solutions that allow multi-rotors to approach speeds of 20 m/s while maneuvering autonomously through hoops. The motion capture system makes this easier by providing the exact pose of the vehicle in the facility, however we intend to study degradation of the tracking solution when using emulated GPS data in the facility. The camera system latency is 5 ms, significantly less than the latency of GPS receivers (typically 100 ms). Therefore the noise and latency patterns of GPS can be emulated and used to study the vehicles response in this scenario.
One of the most significant hurdles in training students in the field of robotics, is the difficulty of embedded development. The Casadi library builds an equation graph that is quite similar to tensor flow used in machine learning. This equation graph can be used to compute gradients and jacobians using automatic differentiation across the graph which makes it an excellent candidate for use in optimal control and trajectory generation.
Another benefit of the Casadi library is that the equation graph can be used to generate efficient C-code that implements the algorithms for deployment to hardware systems. The Casadi library is built using C++ but the interfaces to Python and code generation to C make it quite flexible. Equations can be concisely represented in the Casadi language using the python language, that students can readily understand and modify.
The project will be conducted at the Purdue UAS Research and Test (PURT) facility. PURT is the largest indoor motion capture facility in the world. It is housed in an aircraft hangar at the Purdue airport and consists of 60 Qualisys Oqus7+ motion capture cameras. These cameras can track rigid bodies moving in the facility with 1 mm accuracy. In developing trajectory tracking algorithms, the students will be leveraging state of the art solutions that allow multi-rotors to approach speeds of 20 m/s while maneuvering autonomously through hoops. The motion capture system makes this easier by providing the exact pose of the vehicle in the facility, however we intend to study degradation of the tracking solution when using emulated GPS data in the facility. The camera system latency is 5 ms, significantly less than the latency of GPS receivers (typically 100 ms). Therefore the noise and latency patterns of GPS can be emulated and used to study the vehicles response in this scenario.
Research categories:
Computer Architecture
Preferred major(s):
- Aeronautical and Astronautical Engineering
- Electrical Engineering
- Mechanical Engineering
School/Dept.:
AAE
Professor:
James
Goppert
More information: https://engineering.purdue.edu/PURT
RCAC Anvil REU Internship (x6)
Description:
Internship opportunities:
1. Data analytics: Instrument and perform analysis of scientific application workloads on the Anvil system
2. High Performance Computing (HPC): Extend the Anvil system to burst scientific workflows into the Microsoft Azure cloud
3. Kubernetes: To support science gateways applications, extend Anvil’s Kubernetes-based composable subsystem to use cloud-based Kubernetes clusters
4. Containers to Support Education: Enable the use of large-scale notebook deployments to provide interactive access to Anvil in support of education
Applicants must be U.S. citizens. Open to undergrad students from all backgrounds.
1. Data analytics: Instrument and perform analysis of scientific application workloads on the Anvil system
2. High Performance Computing (HPC): Extend the Anvil system to burst scientific workflows into the Microsoft Azure cloud
3. Kubernetes: To support science gateways applications, extend Anvil’s Kubernetes-based composable subsystem to use cloud-based Kubernetes clusters
4. Containers to Support Education: Enable the use of large-scale notebook deployments to provide interactive access to Anvil in support of education
Applicants must be U.S. citizens. Open to undergrad students from all backgrounds.
Research categories:
Big Data/Machine Learning, Computer Architecture, Internet of Things (IoT), Other
Preferred major(s):
- No Major Restriction
Desired experience:
Linux command line experience preferred. However, programming experience is not a requirement for our REU. We seek students with a range of computational backgrounds and will provide research opportunities appropriate for beginner to advanced levels in computing. Our REU is designed to help you develop these computational skills.
School/Dept.:
RCAC
Professor:
Amanda
Hassenplug
More information: https://www.rcac.purdue.edu/anvil/reu
SCALE System-on-Chip: SoC design, verification, programming, and test
Description:
This project is one of several SCALE SURF research projects. By applying to this project, you can be considered for any of the SCALE projects with one application. See https://nanohub.org/groups/scale/research_su23 to view all of the SCALE SURF research projects for summer 2023.
System on Chip Extension Technologies (SoCET) is a long running chip design team intended primarily for undergraduates to get experience in as many aspects of chip design, fabrication, and test as possible. The team is organized like a small chip design company with sub-teams for logic design, verification, chip-layout, analog design, printed circuit board (PCB) design, test, software, and special research projects in collaboration with research groups in ECE. Special projects include applications in hardware security and GPU design. Based on your interests and background, team leaders will work with you to assign you to an appropriate sub-team or special project. Because of the wide range of projects, the experience and skill requirements for SoCET are flexible. Almost any kind of background in circuit design, logic design, circuit simulation, computer architecture, and microcontroller programming will be useful in some part of the team. For more details on possible projects and sub-teams, see https://engineering.purdue.edu/SoC-Team.
In your application, please specify which of the SCALE technical areas you are most interested in. The
technical areas are:
• Radiation Hardening
• System-on-Chip (indicate this if you are interested in SoCET)
• Heterogenous Integration/ Advanced Packaging
• Program Evaluation
Be sure to name any specific SCALE projects you are interested in, and include information about how you meet the required and desired experience and skills for each of these projects. For US citizen students who are interested: you can become part of the Purdue microelectronics program called SCALE, sponsored by the Department of Defense. In SCALE, you will have opportunities for continuing research (paid or for credit) and industry and government internships throughout your time at Purdue. Please apply to SCALE here: https://research.purdue.edu/scale/.
System on Chip Extension Technologies (SoCET) is a long running chip design team intended primarily for undergraduates to get experience in as many aspects of chip design, fabrication, and test as possible. The team is organized like a small chip design company with sub-teams for logic design, verification, chip-layout, analog design, printed circuit board (PCB) design, test, software, and special research projects in collaboration with research groups in ECE. Special projects include applications in hardware security and GPU design. Based on your interests and background, team leaders will work with you to assign you to an appropriate sub-team or special project. Because of the wide range of projects, the experience and skill requirements for SoCET are flexible. Almost any kind of background in circuit design, logic design, circuit simulation, computer architecture, and microcontroller programming will be useful in some part of the team. For more details on possible projects and sub-teams, see https://engineering.purdue.edu/SoC-Team.
In your application, please specify which of the SCALE technical areas you are most interested in. The
technical areas are:
• Radiation Hardening
• System-on-Chip (indicate this if you are interested in SoCET)
• Heterogenous Integration/ Advanced Packaging
• Program Evaluation
Be sure to name any specific SCALE projects you are interested in, and include information about how you meet the required and desired experience and skills for each of these projects. For US citizen students who are interested: you can become part of the Purdue microelectronics program called SCALE, sponsored by the Department of Defense. In SCALE, you will have opportunities for continuing research (paid or for credit) and industry and government internships throughout your time at Purdue. Please apply to SCALE here: https://research.purdue.edu/scale/.
Research categories:
Computer Architecture, Microelectronics, Nanotechnology, System-on-a-Chip, Other
Preferred major(s):
- Electrical Engineering
- Electrical Engineering Technology
- Computer Engineering
- Computer Engineering Technology
- Computer Science
Desired experience:
Almost any kind of background in circuit design, logic design, circuit simulation, computer architecture, and microcontroller programming will be useful on some part of this project.
School/Dept.:
Electrical and Computer Engineering
Professor:
Mark
Johnson