2023 Research Projects
Projects are posted below; new projects will continue to be posted. To learn more about the type of research conducted by undergraduates, view the archived symposium booklets and search the past SURF projects.
This is a list of research projects that may have opportunities for undergraduate students. Please note that it is not a complete list of every SURF project. Undergraduates will discover other projects when talking directly to Purdue faculty.
You can browse all the projects on the list or view only projects in the following categories:
System-on-a-Chip (5)
Paper-based Microfluidics for Rapid Infectious Disease Diagnostics
Description:
The goal of the project is to design low-cost and user-friendly paper-based point-of-care (POC) diagnostics tests for the detection of a panel of infectious diseases.
These student will be involved directly in the research related to the fabrication and testing of these point-of-care technologies, designed to allow for sensitive, rapid, and repeatable multiplexed detection of a variety of food and waterborne pathogens with high precision and accuracy and minimal sample handling. Target pathogens include parasites such as P. falciparum, (malaria), and Cyclospora Cayetanensis (found in agricultural water that severely lacks detection technologies), along with bacteria-induced foodborne and waterborne infectious diseases such as E. Coli O157:H7, S. Typhimurium, Listeria spp. and Campylobacter Jejuni. These will be aptamer-enabled biosensors, which will be further amenable for the rapid and low cost detection of other diseases, such as inflammation marker panels for Troponin, CRP, IL-6, and TNF-α. Aptamers are DNA molecules with high stability, high affinity for both small molecules and whole-cell pathogens, and are robust when exposed to harsh environments.
The main biorecognition element for the detection of these whole-cell pathogens, responsible for infectious diseases of interest, will be aptamers, which will allow for whole-cell pathogen detection, without amplification or cell lysis. Blood serum samples will be loaded in the sample well, and will diffuse to the four testing areas, each labeled for one individual pathogen. The initially negative testing areas will display a pink color. A positive test for one of the pathogens will be recognized by a change of color from pink to purple. A 3D printed portable imaging box, equipped with an image capture system and embedded color recognition and analysis software will allow for images of the test strips to be taken at constant illumination, on site, at primary care clinics or anywhere at the patient’s home, regardless of time of the day and natural illumination conditions. The portable imaging device will be able to display the test results on the screen. Thus, the detection limit of the diagnostic devices will be pushed down to levels beyond the ones possible with the naked eye, considering the limitation of human vision performance, especially at low illumination levels. A negative test for one pathogen will display an unchanged pink color of the corresponding testing area. We will optimize the device that has already been demonstrated in preliminary work in Stanciu’s group for food samples for E. Coli O157:H7, Listeria monocytogenesis and Salmonella typhimurium, to serum samples for the four pathogens of interests. Ultimately, the project's objective is to establish device performance (detection limit, linear range) .
These student will be involved directly in the research related to the fabrication and testing of these point-of-care technologies, designed to allow for sensitive, rapid, and repeatable multiplexed detection of a variety of food and waterborne pathogens with high precision and accuracy and minimal sample handling. Target pathogens include parasites such as P. falciparum, (malaria), and Cyclospora Cayetanensis (found in agricultural water that severely lacks detection technologies), along with bacteria-induced foodborne and waterborne infectious diseases such as E. Coli O157:H7, S. Typhimurium, Listeria spp. and Campylobacter Jejuni. These will be aptamer-enabled biosensors, which will be further amenable for the rapid and low cost detection of other diseases, such as inflammation marker panels for Troponin, CRP, IL-6, and TNF-α. Aptamers are DNA molecules with high stability, high affinity for both small molecules and whole-cell pathogens, and are robust when exposed to harsh environments.
The main biorecognition element for the detection of these whole-cell pathogens, responsible for infectious diseases of interest, will be aptamers, which will allow for whole-cell pathogen detection, without amplification or cell lysis. Blood serum samples will be loaded in the sample well, and will diffuse to the four testing areas, each labeled for one individual pathogen. The initially negative testing areas will display a pink color. A positive test for one of the pathogens will be recognized by a change of color from pink to purple. A 3D printed portable imaging box, equipped with an image capture system and embedded color recognition and analysis software will allow for images of the test strips to be taken at constant illumination, on site, at primary care clinics or anywhere at the patient’s home, regardless of time of the day and natural illumination conditions. The portable imaging device will be able to display the test results on the screen. Thus, the detection limit of the diagnostic devices will be pushed down to levels beyond the ones possible with the naked eye, considering the limitation of human vision performance, especially at low illumination levels. A negative test for one pathogen will display an unchanged pink color of the corresponding testing area. We will optimize the device that has already been demonstrated in preliminary work in Stanciu’s group for food samples for E. Coli O157:H7, Listeria monocytogenesis and Salmonella typhimurium, to serum samples for the four pathogens of interests. Ultimately, the project's objective is to establish device performance (detection limit, linear range) .
Research categories:
Chemical Catalysis and Synthesis, Internet of Things (IoT), Medical Science and Technology, Nanotechnology, System-on-a-Chip
Preferred major(s):
- No Major Restriction
Desired experience:
General chemistry or biochemistry laboratory training.
School/Dept.:
Materials Engineering
Professor:
Lia
Stanciu
More information: https://lia-stanciu.squarespace.com/
Quantum Characterization Setup Software Development
Description:
This research project focuses on the development of software algorithms for automated analysis of single photon emitters in silicon nitride nanopillars. The students role will be to develop these algorithms to help produce large datasets to be used in machine learning studies and in basic process development studies of emitters generated though the annealling of SiN/SiO nanopillars.
Research categories:
Big Data/Machine Learning, Material Processing and Characterization, Nanotechnology, System-on-a-Chip
Preferred major(s):
- No Major Restriction
Desired experience:
Strong python programming skills and algorithm development skills. Additionally, image processing skills are a plus!
School/Dept.:
Electrical and Computer Engineering (ECE)
Professor:
Alexander
Kildishev
SCALE Heterogeneous Integration/ Advanced Packaging: 3D Cryogenic Packaging for Superconducting Computing
Description:
This project is one of several SCALE SURF research projects. SCALE projects are restricted to students who are U.S. Citizens. By applying to this project, you can be considered for any of the SCALE projects with one application. See https://nanohub.org/groups/scale/research_su23 to view all of the SCALE SURF research projects for summer 2023.
In 2017, a large-scale, 3D integrated quantum processor was demonstrated by MIT Lincoln Laboratory using heterogeneous 3D integration to create an architecture that enables the use of the third dimension without sacrificing qubit performance [D. Rosenberg, et al., Nature 2017]. In these quantum applications, conventional Sn-based solder bumps are not reliable while Indium and bismuth-based solders are promising for 3D integration at low temperatures. In this topic, new cryogenic compatible packaging materials and cryogenic superconducting multi-chip bonding techniques are needed to further explore and investigate the microelectronics devices and packages at low/cryogenic temperatures.
Reference: Rosenberg, D., et al. "3D integrated superconducting qubits." npj quantum information 3.1 (2017): 1-5.)
In your application, please specify which of the SCALE technical areas you are most interested in. The technical areas are:
• Radiation Hardening
• System-on-Chip
• Heterogenous Integration/ Advanced Packaging
• Program Evaluation
Be sure to name any specific SCALE projects you are interested in, and include information about how you meet the required and desired experience and skills for each of these projects.
For US citizen students who are interested: you can become part of the Purdue microelectronics program called SCALE, sponsored by the Department of Defense. In SCALE, you will have opportunities for continuing research (paid or for credit) and industry and government internships throughout your time at Purdue. Please apply to SCALE here: https://research.purdue.edu/scale/.
In 2017, a large-scale, 3D integrated quantum processor was demonstrated by MIT Lincoln Laboratory using heterogeneous 3D integration to create an architecture that enables the use of the third dimension without sacrificing qubit performance [D. Rosenberg, et al., Nature 2017]. In these quantum applications, conventional Sn-based solder bumps are not reliable while Indium and bismuth-based solders are promising for 3D integration at low temperatures. In this topic, new cryogenic compatible packaging materials and cryogenic superconducting multi-chip bonding techniques are needed to further explore and investigate the microelectronics devices and packages at low/cryogenic temperatures.
Reference: Rosenberg, D., et al. "3D integrated superconducting qubits." npj quantum information 3.1 (2017): 1-5.)
In your application, please specify which of the SCALE technical areas you are most interested in. The technical areas are:
• Radiation Hardening
• System-on-Chip
• Heterogenous Integration/ Advanced Packaging
• Program Evaluation
Be sure to name any specific SCALE projects you are interested in, and include information about how you meet the required and desired experience and skills for each of these projects.
For US citizen students who are interested: you can become part of the Purdue microelectronics program called SCALE, sponsored by the Department of Defense. In SCALE, you will have opportunities for continuing research (paid or for credit) and industry and government internships throughout your time at Purdue. Please apply to SCALE here: https://research.purdue.edu/scale/.
Research categories:
Advanced Packaging, Heterogeneous Integration, Material Processing and Characterization, Microelectronics, Nanotechnology, System-on-a-Chip
Preferred major(s):
- Electrical Engineering
- Materials Engineering
- Mechanical Engineering
Desired experience:
1. Microelectronics, micro/nanotechnology courses
2. Clean room fabrication experience
3. Enthusiasm for material fabrication and characterizations
4. Familiar with SEM, TEM analysis
School/Dept.:
ME
Professor:
Tiwei
Wei
More information: https://alphalab-purdue.org/
SCALE Heterogeneous Integration/ Advanced Packaging: Glass Interposer Development for 3D Heterogenous Integration
Description:
This project is one of several SCALE SURF research projects. SCALE projects are restricted to students who are U.S. Citizens. By applying to this project, you can be considered for any of the SCALE projects with one application. See https://nanohub.org/groups/scale/research_su23 to view all of the SCALE SURF research projects for summer 2023.
Interposer is one of the most potential solutions for future 3D integration with ultrafine pitch. Silicon interposer has been developed in both industry and academia. However, silicon interposer has limitations, such as low productivity due to limited wafer size, extra expensive semiconductor fabrication processes, and poor electrical properties like insert loss and signal crosstalk. On the contrary, glass can be one kind of promising material as an interposer because of its excellent properties, such as good electrical resistivity, relatively low CTE compared to organic material, and possible high productivity with big panel sizes provided by glass suppliers.
Recent research studies have mainly focused on three challenges in glass interposer technology: (1) formation of the fine pitch via, which is more difficult than through silicon via (TSV) due to the unfavorable etching process ; (2) via metallization and via filling process, which become much more complicated because of the rough morphology of TGV surface, and difficulty to fill the tapered via through Damascus electroplating; (3) reliability concern, which is caused by brittleness and poor mechanical strength of glass.
Through glass via fabrications
Reference: Wei, T. W., Cai J.*, et al. Performance and reliability study of TGV interposer in 3D integration[C]//2014 IEEE 16th Electronics Packaging Technology Conference (EPTC). IEEE, 2014: pp. 601-605.
In your application, please specify which of the SCALE technical areas you are most interested in. The technical areas are:
• Radiation Hardening
• System-on-Chip
• Heterogenous Integration/ Advanced Packaging
• Program Evaluation
Be sure to name any specific SCALE projects you are interested in, and include information about how you meet the required and desired experience and skills for each of these projects.
For US citizen students who are interested: you can become part of the Purdue microelectronics program called SCALE, sponsored by the Department of Defense. In SCALE, you will have opportunities for continuing research (paid or for credit) and industry and government internships throughout your time at Purdue. Please apply to SCALE here: https://research.purdue.edu/scale/.
Interposer is one of the most potential solutions for future 3D integration with ultrafine pitch. Silicon interposer has been developed in both industry and academia. However, silicon interposer has limitations, such as low productivity due to limited wafer size, extra expensive semiconductor fabrication processes, and poor electrical properties like insert loss and signal crosstalk. On the contrary, glass can be one kind of promising material as an interposer because of its excellent properties, such as good electrical resistivity, relatively low CTE compared to organic material, and possible high productivity with big panel sizes provided by glass suppliers.
Recent research studies have mainly focused on three challenges in glass interposer technology: (1) formation of the fine pitch via, which is more difficult than through silicon via (TSV) due to the unfavorable etching process ; (2) via metallization and via filling process, which become much more complicated because of the rough morphology of TGV surface, and difficulty to fill the tapered via through Damascus electroplating; (3) reliability concern, which is caused by brittleness and poor mechanical strength of glass.
Through glass via fabrications
Reference: Wei, T. W., Cai J.*, et al. Performance and reliability study of TGV interposer in 3D integration[C]//2014 IEEE 16th Electronics Packaging Technology Conference (EPTC). IEEE, 2014: pp. 601-605.
In your application, please specify which of the SCALE technical areas you are most interested in. The technical areas are:
• Radiation Hardening
• System-on-Chip
• Heterogenous Integration/ Advanced Packaging
• Program Evaluation
Be sure to name any specific SCALE projects you are interested in, and include information about how you meet the required and desired experience and skills for each of these projects.
For US citizen students who are interested: you can become part of the Purdue microelectronics program called SCALE, sponsored by the Department of Defense. In SCALE, you will have opportunities for continuing research (paid or for credit) and industry and government internships throughout your time at Purdue. Please apply to SCALE here: https://research.purdue.edu/scale/.
Research categories:
Advanced Packaging, Heterogeneous Integration, Material Modeling and Simulation, Material Processing and Characterization, Microelectronics, Nanotechnology, System-on-a-Chip
Preferred major(s):
- Electrical Engineering
- Mechanical Engineering
- Materials Engineering
Desired experience:
1. Microelectronics, micro/nanotechnology courses
2. Clean room fabrication experience
3. Enthusiasm for material fabrication and characterizations
4. Familiar with SEM, and TEM analysis.
School/Dept.:
ME
Professor:
Tiwei
Wei
More information: https://alphalab-purdue.org/
SCALE System-on-Chip: SoC design, verification, programming, and test
Description:
This project is one of several SCALE SURF research projects. By applying to this project, you can be considered for any of the SCALE projects with one application. See https://nanohub.org/groups/scale/research_su23 to view all of the SCALE SURF research projects for summer 2023.
System on Chip Extension Technologies (SoCET) is a long running chip design team intended primarily for undergraduates to get experience in as many aspects of chip design, fabrication, and test as possible. The team is organized like a small chip design company with sub-teams for logic design, verification, chip-layout, analog design, printed circuit board (PCB) design, test, software, and special research projects in collaboration with research groups in ECE. Special projects include applications in hardware security and GPU design. Based on your interests and background, team leaders will work with you to assign you to an appropriate sub-team or special project. Because of the wide range of projects, the experience and skill requirements for SoCET are flexible. Almost any kind of background in circuit design, logic design, circuit simulation, computer architecture, and microcontroller programming will be useful in some part of the team. For more details on possible projects and sub-teams, see https://engineering.purdue.edu/SoC-Team.
In your application, please specify which of the SCALE technical areas you are most interested in. The
technical areas are:
• Radiation Hardening
• System-on-Chip (indicate this if you are interested in SoCET)
• Heterogenous Integration/ Advanced Packaging
• Program Evaluation
Be sure to name any specific SCALE projects you are interested in, and include information about how you meet the required and desired experience and skills for each of these projects. For US citizen students who are interested: you can become part of the Purdue microelectronics program called SCALE, sponsored by the Department of Defense. In SCALE, you will have opportunities for continuing research (paid or for credit) and industry and government internships throughout your time at Purdue. Please apply to SCALE here: https://research.purdue.edu/scale/.
System on Chip Extension Technologies (SoCET) is a long running chip design team intended primarily for undergraduates to get experience in as many aspects of chip design, fabrication, and test as possible. The team is organized like a small chip design company with sub-teams for logic design, verification, chip-layout, analog design, printed circuit board (PCB) design, test, software, and special research projects in collaboration with research groups in ECE. Special projects include applications in hardware security and GPU design. Based on your interests and background, team leaders will work with you to assign you to an appropriate sub-team or special project. Because of the wide range of projects, the experience and skill requirements for SoCET are flexible. Almost any kind of background in circuit design, logic design, circuit simulation, computer architecture, and microcontroller programming will be useful in some part of the team. For more details on possible projects and sub-teams, see https://engineering.purdue.edu/SoC-Team.
In your application, please specify which of the SCALE technical areas you are most interested in. The
technical areas are:
• Radiation Hardening
• System-on-Chip (indicate this if you are interested in SoCET)
• Heterogenous Integration/ Advanced Packaging
• Program Evaluation
Be sure to name any specific SCALE projects you are interested in, and include information about how you meet the required and desired experience and skills for each of these projects. For US citizen students who are interested: you can become part of the Purdue microelectronics program called SCALE, sponsored by the Department of Defense. In SCALE, you will have opportunities for continuing research (paid or for credit) and industry and government internships throughout your time at Purdue. Please apply to SCALE here: https://research.purdue.edu/scale/.
Research categories:
Computer Architecture, Microelectronics, Nanotechnology, System-on-a-Chip, Other
Preferred major(s):
- Electrical Engineering
- Electrical Engineering Technology
- Computer Engineering
- Computer Engineering Technology
- Computer Science
Desired experience:
Almost any kind of background in circuit design, logic design, circuit simulation, computer architecture, and microcontroller programming will be useful on some part of this project.
School/Dept.:
Electrical and Computer Engineering
Professor:
Mark
Johnson