STARS

The semiconductor design track gives students a rare undergraduate experience in designing, verifying, and submitting a digital integrated circuit for fabrication (tape-out). The longer-term goal is to equip students to be able to enter semiconductor design and verification internships in industry after their sophomore year. Students are not expected to already have much if any prior circuit design experience. The design track spans six weeks. In week one, students will practice discrete circuit construction and use of bench instrumentation. In week two, students will design, simulate, and create FPGA prototypes of combinational logic functions such as multiplexers, adders, and decoders. In week three, students move on to sequential functions such as state machines, counters, and shift registers. All such functions are essential building blocks for more complex systems. In week four, students will be guided in using rigorous block diagrams to plan more designs based on many instances of functions implemented previously. Small teams will be formed and led by undergraduate teaching assistants who will guide team members in planning their final design. In week five, the teams will implement the blocks for their design. Finally, in week six, students will integrate their designs, and run the designs through a place and route and physical verification process. Later, teaching assistants will integrate all designs into a single pad frame and complete the tape-out. A few months later, the resulting chips will be returned to students mounted on printed circuit boards (PCBs) and guidance will be provided for testing of the designs. Staff for the design track include one graduate teaching assistant, eight undergraduate teaching assistants, two lecturers, and two laboratory coordinators led by Dr. Mark C Johnson.

Semiconductor manufacturing track will focus on skill development on chip fabrication, semiconductor materials and device characterization. Students will be learning about cleanroom safety, substrate engineering, oxidation, lithography, thin film deposition (physical vapor deposition and atomic layer deposition), reactive ion etching and wet chemicals-based cleaning and etching, thermal diffusion and annealing, ion implantation, chemical mechanical polishing (CMP) and basic integration of MOSCAP and CMOS devices. They will be trained through online and in-person instruction, interactive discussions, virtual and in-person hands on training in vFabLab and cleanroom, respectively and video tutorials. For material characterization they will be learning about atomic force microscopy, x-ray diffraction analysis, secondary ion mass spectroscopy, scanning electron microscopy, x-ray photoelectron spectroscopy and transmission electron microscopy. For device characterization they will be learning about MOSCAP and MOSFET performance and reliability measurement and analysis. Profs. Muhammad Hussain (ECE), Rahim Rahimi (MSE), Thomas Beecham III (ME and ChE) and Muhammad Alam (ECE) will be serving as instructors with 5 graduate teaching assistants and 1 senior research scientist.

As of May 2023, we have received STARS support from Intel, Cisco, Synopsys, L3Harris, Sk Hynix, SkyWater, Texas Instruments, Western Digital, TSMC and Mediatek. We are seeking additional sponsors to ensure at least 75 students can receive this training in summer 2023. We are also looking for support for summer 2024 and beyond. If your company would like to sponsor STARS, please contact Cristina Farmus. Additional details available in our sponsorship documentation (DOCX).