December 5, 2023

International Workshop for Advanced System Integration and Packaging

Event Date: December 5, 2023
Location: Purdue University Shively Club at Ross-Ade Stadium
Priority: No
College Calendar: Show
Organized by Purdue University's Atalla Institute for Advanced System Integration and Packaging (ASIP) in partnership with ARI, host of the Si Crossroads ME Commons Hub, imec USA, Cadence and Osaka University.

December 5-6, 2023

As transistor scaling according to Moore’s law slows, future applications will require novel system integration solutions to achieve performance, power, and cost tradeoffs while ensuring efficient power conversion and delivery, signal and power integrity, sustainability, testability, and security goals. Increasingly, future electronic systems for computing, mobile communications, IoT, automotive, defense and biological applications will rely on advanced integration of separately manufactured chiplets into a 2.5D/3D System-in-Package (SiP).

At this workshop, internationally acclaimed industry and academic leaders will address the challenges to research, “lab-to-fab” translation and workforce necessary to build the future microelectronic systems. The challenges include system architectural and physical design enabled by multiphysics modeling tools, high-density interposers and substrates, process development for interconnect pitch scaling, and thermal solution design, all while meeting the reliability and manufacturing yield goals. The workshop will bring together IDMs, fabless companies, EDA companies, tool vendors, materials suppliers, OSATs, National Labs and university academics to describe current capabilities, identify future challenges, and to develop partnerships in pursuit of future programmatic opportunities.

Highlights

  • Talks by senior technical leaders from Intel, SK hynix, imec, AMD, IBM and Joint2 Consortium of Japan
  • Four panel sessions covering (1) Chips and SiPs (2) Application Drivers and Advanced System Integration (3) Foundational Ecosystem (4) Opportunities and Partnerships
  • Many other confirmed panelists including from Cadence and Applied Materials
  • Nearly 10 Japanese material suppliers will participate including AGC, Resonac, Mitsubishi Chemicals, Okuno Chemical, Daicel Corporation, Towa Corporation, Horiba Instruments and Yamato Scientific
  • Sessions highlighting Purdue ASIP research and education
  • Student poster sessions highlighting Purdue research and education
  • Tour of Purdue’s Birck Nanotechnology Center and the Scifres Cleanroom

Agenda

Hotel Information
Parking Information (PDF)

December 5, Tuesday

8:00-8:30 AM

Breakfast

8:30-9:00 AM

Welcome

8:30 AM - Welcome

8:40 AM - IEDC overview

8:50 AM - Purdue Semiconductors overview

9:00-9:30 AM

Keynote 1

Dr. Jaesik Lee, VP Package Engineering, SK hynix

9:30-10:15 AM

Purdue ASIP Institute Research Highlights

10:15-10:30 AM

Break

10:30-11:45 AM

Technology Highlights Panel 1: Advanced Packaging – Chips and SiPs

  • Opening presentation – Dr. Dale McHerron, Chief Strategist, Chiplet and Advanced Packaging, IBM
  • Presentations
    • Dr. Yoji Nakajima, VP Global Technology and Strategy, AGC
    • Kazuyuki Mitsukura, Technical Director, Resonac America
    • Bob Patti, President, NHanced Semiconductors
    • Babu Mandava, President and CEO, 3dGS
    • Lee Smith, Business Development Director, Applied Materials
  • Panel discussion

11:45 AM-2:00 PM

Lunch + Tour of the Birck Nanotechnology Center Facility

2:00-2:30 PM

 Keynote 2 – Dr. Xin Wu, Corporate VP, Silicon Technology, AMD

2:30-3:00 PM

Keynote 3 – Dr. Geert Van der Plas, Scientific Director, imec

3:15-3:30 PM

Break

3:15-4:30 PM

Technology Highlights Panel 2: Application Drivers and Advanced System Integration

  • Opening presentation, Dr. Sujit Sharan, Senior Director Advanced Design & Technology Solutions, Intel Corporation
  • Presentations
    • Dr. John Park, Product Management Group Director for IC packaging and cross-platform solutions, Cadence
    • Dr. Timothy Lee, Boeing Technical Fellow, Boeing
    • Dr. Hasan Sharifi, Department Manager, HRL
    • Dr. Vaishnav Srinivas, Senior Director of Engineering, Qualcomm
  • Panel discussion

4:30-5:00 PM

Purdue Education and Workforce Highlights
5:00-5:15 PM

30 seconds student overviews of posters

5:15-6:30 PM

Reception + Student Posters

6:30 PM

Dinner

December 6, Wednesday

8:00-8:30 AM

Breakfast

8:30-9:00 AM

Keynote 4: Joint2 Consortium Japan – Hidenori Abe, Senior Director and Head of R&D Center Electronic Business, Resonac

9:00-10:15 AM

Technology Highlights Panel 3: Advanced Packaging - Foundational Ecosystem

  • Presentations
    • Professor Katsuaki Suganuma, Director of Flexible 3D System Integration Lab, Osaka University
    • Nobuo Kakehi, Senior Fellow and CTO, Yamato Scientific
    • Kosuke Matsumoto, Deputy Department Manager, Horiba STEC Co.
    • Hiroyuki Niwa, General Manager, Electronic and Imaging Materials, Toray Industries
    • Chris Masuyama, New Business Development Manager, Towa USA Co.
    • Katsuhiko Hidaka, Senior Manager Global Semiconductor Packaging, Mitsubishi Chemical Co.
    • Haruki Nagamura, Advanced R&D Laboratories, Okuno Chemical Industry Co.  
  • Panel discussion

10:15-10:30 AM

Break

10:30-11:45 AM

Panel 4: Opportunities and Partnerships

  • Opening presentation - Professor Subramanian Iyer, Director of NAPMP, CHIPS R&D Office
  • Presentations
    • Dr. Arianna Gleason-Holbrook, Deputy Director High Energy Density Science Division, SLAC National Accelerator Laboratory
    • Mike O'Brien, Senior Relationship Director, CHIPS Program Office
    • Dr. George Orji, Deputy Director of NAPMP, CHIPS R&D Office
    • Dr. Jonathan Prange, R&D Program Manager, imec US
    • Professor Bahgat Sammakia, VP Research, Binghamton University
    • Professor Katsuaki Suganuma, Director of Flexible 3D System Integration Lab, Osaka University
  • Panel discussion

11:45 AM - 12:00 PM

Closing

12:00-1:00 PM

Lunch

About Microelectronics Research and Education at Purdue University:

College of Engineering at Purdue University is ranked 4th in the US and graduates more engineers than the top three ranked institutions combined. Purdue’s excellence at scale is exemplified by the many national and international microelectronic research centers at Purdue that have received over $250 million in research funding. Specifically, in Advanced System Integration and Packaging, Purdue hosts five centers that together conduct nearly $90 million in research. Purdue University, through its expert faculty, is actively involved in guiding the formulation of the CHIPS Act R&D programs and is vigorously engaged with industry partners on all elements of CHIPS Act programs.

Complementary to the research mission, Purdue created the nation’s first MS degree program in semiconductors, with more than 55 Purdue faculty members teaching over 100 courses on semiconductors and advanced packaging. Purdue’s educational innovations to motivate talented undergraduate students to pursue careers in semiconductors include the freshmen-level seminar course “Changing the World with Chips - Introduction to Semiconductors,” and a unique eight-week hands-on experience in chip design and fabrication termed “Summer Training, Awareness, and Readiness for Semiconductors (STARS).” More information at https://engineering.purdue.edu/semiconductors.

Contact: Shelby Vibbert or Ganesh Subbarayan

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