James R. Eaton Jr. completed his bachelor's degree in 1958 and worked at the Allen-Bradley Company. Returning to Purdue in 1962, he worked summers at IBM's T.J. Watson Research Laboratory, the Autonetics Divison of North American Aviation, and the RCA David Sarnoff Research Laboratory. He completed his doctorate in 1967, and became a member of the technical staff at Hewlett-Packard Laboratories.

After investigating magnetic memory technologies for use in electronic instrumentation, Eaton switched to development of semiconductor memory technology. He was co-developer of an experimental dynamic bipolar memory cell utilizing a 4-layer diode structure, an early investigator of the charge conservative MOS transistor model, and the senior designer of HP's first dynamic RAM. This led to the co-authoring of the U.S. patent, "An x-y addressable dynamic memory cell." He was also the senior designer of HP's state-of-the-art 32 kilobit electrically alterable ROM and pioneered 36 V NMOS boot-strapping techniques.

He became section manager in the design technology laboratory and mentored the development of MOS standard cell design and place-and-route technologies. In 1991 he was named technical contributor in the Design Technology Center of the Integrated Circuits Business Division where he developed the mathematical theory of optimization applied to design of CMOS logic gates and co-developed the cell design methodology used in the majority of HP-designed integrated circuits. He also developed the HP on-chip Electrostatic Discharge (ESD) protection system.

In 1997 he was named to his present position and concentrates on fundamental mathematical issues of optimization, signal integrity in submicron CMOS technology, and the personal/technical interactions that lead to successful design projects. A member of the IEEE, National Association for the Advancement of Science, and Sigma Xi, he enjoys sail boat racing and photography.