Abstract

Microelectronics system architecture design is at the cusp of a technological shift with pervasive application of intelligence,  modular chiplet integration enabling hybrid multi-die architecture, with ensuing security concerns with untrusted chiplets including DoS, snooping and side channels. The corresponding package-level hardware trends include 2.5D system in package with silicon or organic interposers, thinned stacked dies, and photonic integration. Complementing these system architecture and packaging trends are beyond CMOS technologies and BEOL innovations including novel metal and dielectric materials, and integrating novel devices and technologies at the intermediate interconnect layers. This panel will explore the drivers behind the technological trends and the research priorities that must be addressed to enable the microchips of the future.

Hosted by College of Engineering, Mechanical Engineering, and Electrical and Computer Engineering

Moderator:

Carol Handwerker, Reinhardt Schuhmann Jr. Professor of Materials Engineering

Panelists:

• Ravi Mahajan, Intel Fellow, High Density Interconnect Pathfinding, Assembly Technology, Intel Corporation ASME Fellow, IEEE Fellow; VP of Publications & Managing Editor-in-Chief of the IEEE Transactions of the CPMT
• Zhihong Chen, Professor of Electrical and Computer Engineering
• Anand Raghunathan, Silicon Valley Professor of Electrical and Computer Engineering
• Ganesh Subbarayan-Shastri, Professor of Mechanical Engineering

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