In pursuit of finer and finer resolution: from Abbe’s theory of microscopy to high-NA EUV lithography
![]()
Abstract:
Photolithography in today’s semiconductor manufacturing makes use of projection imaging whose working principle can be traced back to the work of Ernst Abbe in microscopy. In 1873, Abbe stated that the resolution limit of projection imaging was P_min=0.5 λ⁄NA with P_min being the minimum pitch of a grating, λ the illuminating wavelength, and NA the numerical aperture of the imaging optics. Today, resolution in projection lithography is given by the equation HP_min=k_1 λ⁄NA where HP_min is the minimum printable half-pitch of a periodic pattern and k_1 is a numerical factor with an absolute minimum value of 0.25. Unlike microscopy, photolithography forms patterns in a photoresist and must result in stringent control of feature dimensions, good feature integrity, and high accuracy in feature placement. These factors depend on, besides the superb mechatronics of the exposure tool, the quality of the imaging optics, capability of the photoresist, and sophistication of the photomask combined with the way it is illuminated. They work together to determine the k_1 and the HP_min in high-volume manufacturing (HVM).
Following the Abbe equation of reducing λ, increasing NA, and gradually lowering k_1, projection lithography began with unit-magnification wafer scanners in the 1970s and was advanced with the arrival of Hg g-line (436 nm) wafer steppers with about 0.8 µm in practical resolution. Wafer steppers using the Hg i-line (365 nm) wavelength came to wide use starting about 1990. Combined with off-axis illumination which lowered k_1, i-line lithography was able to reach below 0.35 µm in resolution. Deep ultraviolet (DUV) lithography at the 248-nm wavelength provided by the KrF excimer laser came next, entering into production at about 1997 for the 0.25-µm logic node (with 0.3-µm minimum half-pitch), followed by the adoption of 193-nm ArF lithography, whose initial use in manufacturing, for the 0.13-µm technology node, took place in 2001. 193-nm immersion lithography, with its working principle already elucidated by Abbe who also designed immersion optics for microscopy, entered HVM with NA=1.2 in 2007 at the 45-nm node. This was followed by the 28, 20, 14, and 10-nm nodes with NA=1.35, the latter three employing multiple patterning. EUV lithography entered into HVM in 2019 and printed dense lines of 20-nm half-pitch that year. With the arrival of EUV wafer scanners with NA=0.55 in 2024, dense lines of less than 10-nm half-pitch can now be printed.
Advances in 193-nm immersion lithography have enabled k_1=0.26 in HVM. Scientists and engineers are actively working on lowering the k_1-factor further in EUV lithography which is now below 0.4. What happens after that? A hyper-NA EUV exposure tool with NA=0.75 is being contemplated to achieve even finer resolution in photolithography for patterning semiconductor devices.
Biography:
Anthony (Tony) Yen is VP and Head of the Technology Development Center at ASML, leading a global team to work on long-term technological directions in semiconductors and accompanying patterning solutions in close collaboration with other organizations within ASML, imec, and universities. He also serves as a Distinguished Adjunct Professor in the College of Engineering, Purdue University. Tony received his BSEE degree from Purdue University and his SM, EE, PhD, and MBA degrees from MIT. From 1991 to 1997, he was a Member of the Technical Staff at Texas Instruments. From 1997 to 2003 and again from 2006 to 2017, he was with TSMC where he led the development of optical lithography processes and of EUV lithography for high-volume manufacturing. Tony is a recipient of the Outstanding Electrical and Computer Engineer Award from Purdue’s ECE School. He is a Fellow of the IEEE and a recipient of the IEEE Cledo Brunetti Award and the IEEE EDS J. J. Ebers Award. He is also a Fellow of SPIE and a recipient of its Frits Zernike Award for Microlithography.
The event is also in partnership with IEEE Purdue Chapter and Purdue Semiconductor Student Alliance (SSA).