Dr. Joel S. Emer
Intel Fellow and Director of Microarchitecture Research, Intel Corporation
"I have long believed in the aphorism that 'success is when opportunity meets preparation', and my excellent education and mentors at Purdue were pivotal in preparing me for my career."
Joel Emer is an Intel Fellow and Director of Microarchitecture Research at Intel in Hudson, Mass. He also is a Professor of the Practice at the Massachusetts Institute of Technology, where he teaches the graduate advanced computer architecture class, and conducts research in high-speed modeling of processor performance. He earned his BSEE with highest honors in 1974, his MSEE in 1975, both from Purdue University; and his Ph.D. in electrical engineering from the University of Illinois in 1979.
After completing his Ph.D., he worked at Digital Equipment Corporation and then Compaq Computer. At Digital he was a member of the small corporate taskforce that proposed Digital's Alpha processor strategy. Alphas were the highest speed processors of the 1990s, and were instrumental in decoding the human genome.
Emer has been cited for innovative design contributions to a variety of Alpha processors. He was noted for “nearly single handedly” creating Digital's corporate performance modeling methodology. His research record includes pioneering efforts in simultaneous multithreading, now widely used in microprocessors including the Intel Core i7. He also developed groundbreaking techniques for the analysis of the architectural impact of soft errors and made seminal contributions to the quantitative approach to processor evaluation. His techniques have established industry-wide practices and were the basis for the major textbook in the field.
Emer holds more than 25 patents and has published more than 35 papers, six of which have been selected for various “best of” recognitions. He authored a chapter on performance modeling techniques for an upcoming textbook. He is a highly sought after speaker, and has given more than 10 distinguished lectures and keynote addresses.
He also served on the advisory board for several computer science departments; is a member of Eta Kappa Nu and Tau Beta Pi; and a Fellow of both the ACM and the IEEE. In 2009, Emer was the recipient of the prestigious Eckert-Mauchly award, an ACM/IEEE joint award, and the highest professional recognition, for contributions in computer architecture.
After completing his Ph.D., he worked at Digital Equipment Corporation and then Compaq Computer. At Digital he was a member of the small corporate taskforce that proposed Digital's Alpha processor strategy. Alphas were the highest speed processors of the 1990s, and were instrumental in decoding the human genome.
Emer has been cited for innovative design contributions to a variety of Alpha processors. He was noted for “nearly single handedly” creating Digital's corporate performance modeling methodology. His research record includes pioneering efforts in simultaneous multithreading, now widely used in microprocessors including the Intel Core i7. He also developed groundbreaking techniques for the analysis of the architectural impact of soft errors and made seminal contributions to the quantitative approach to processor evaluation. His techniques have established industry-wide practices and were the basis for the major textbook in the field.
Emer holds more than 25 patents and has published more than 35 papers, six of which have been selected for various “best of” recognitions. He authored a chapter on performance modeling techniques for an upcoming textbook. He is a highly sought after speaker, and has given more than 10 distinguished lectures and keynote addresses.
He also served on the advisory board for several computer science departments; is a member of Eta Kappa Nu and Tau Beta Pi; and a Fellow of both the ACM and the IEEE. In 2009, Emer was the recipient of the prestigious Eckert-Mauchly award, an ACM/IEEE joint award, and the highest professional recognition, for contributions in computer architecture.