Purdue ECE part of new Intel Labs Resilient Architectures and Robust Electronics (RARE) Multi-University Research Center
Purdue University is part of a new initiative from Intel Labs' University Research & Collaboration Office (URC). The multi-university research center called Resilient Architectures and Robust Electronics (RARE) will focus on assessing and improving the resiliency, reliability, and security of Intel® hardware and software, including the security of Intel® silicon integrated circuits. In addition, all research will be made public to the general semiconductor industry.
The RARE center launched in Q4 of 2021 and will operate for three years. The main research areas include:
Error characteristics of computing: Indentify silicon failure mechanisms that result in computer errors of various types and provide mitigations of and response to these conditions.
- New solutions, techniques, and mechanisms to detect compute failure conditions: Improve the handling of compue failures by providing new detection and mitigation mechanisms.
- Research and tools for side-channels-free and fault-tolerant processors: Advance research related to speculative execution and other security issues such as fault injections attacks.
- Novel hardware mitigations: Advance secure, confidential computing with new concepts learned from a clean slate processor design.
"Securing Intel technology and increasing the reliability of our semiconductors is our top priority," said Frank McKeen, senior principal engineer, Intel Labs. "Environmental anomalies and fault injection attacks, for example, are becoming more common, and there is a need to increase error detection and discover new ways to recover from errors. Through collaborating with these leading academic researchers, we will find solutions and novel approaches to these important industry-wide electronic security challenges."
Academic researchers from 10 leading universities were selected to develop new capabilities to help increase the reliability and security of computing technologies. Research areas include systematic mitigation of error conditions and faults and associated impacts on future CPU architectures and implementations. These include faults caused by natural radiation, aging, random effects, noisy environments, and electronic glitches. In addition, research will also investigate intentionally caused faults such as fault injection attacks.
Shreyas Sen, Elmore Associate Professor of Electrical and Computer Engineering and director of the Sensing and Communication (SPARC) Research Lab, is leading a project entitled “Understanding in the Photonic Side-Channel: White-Box Model and Low-Overhead Generic Defenses.”
Sen says he is excited to be part of this opportunity.
“This will allow us to continue our physics-driven white-box approach to physical security vulnerabilities, previously established, through strong multi-year collaboration with Intel, on power and EM side-channels to new domains such as photonic side-channels,” he says. “Such a ground-up approach of understanding the leakage mechanism will allow killing the leakages at its source, with the highest protection and lowest power-performance-area overheads.
The SparcLab team is focused on developing an in-depth theoretical understanding of advanced physical side-channel leakage mechanisms from cryptographic integrated circuits, i.e., going from a black-box to a physics-driven white-box model of leakage. Such deep knowledge then allows the development of new techniques of stopping the leakage at the source itself, using physical-, circuit-, or system-level techniques with the lowest overhead possible. This project aims to explore the fundamentals of a photonic side-channel among other advance physical side-channels.