System-On-Chip Design

ECE69500

Credit Hours:

3

Description:

The incessant drive of Moore's law has created an era where most electronic systems contain chips that integrate various (hitherto discrete) components such as microprocessor, DSPs, dedicated hardware processing engines, memories, and interfaces to I/O devices and off-chip storage. Most electronic systems today - cell phones, iPods, set-top boxes, digital TVs, automobiles - contain at least one such "System-on-chip". Designing System-on-chips is a highly complex process. Before entering the traditional VLSI implementation process (RTL, logic & physical design), design teams need to perform the challenging tasks of developing a functional specification, partitioning and mapping of functions onto hardware components and software, design of a communication architecture to interconnect the components, functional/performance/power analysis and validation, and more. This course will present students with an insight into the earlier stages of the System-on-chip design process (what happens before you get down to RTL, gates, transistors, and wires). In addition to the conceptual foundations, this course will also involve significant hands-on assignments and/or a project that will give students an exposure to state-of-the-art design methodologies and platforms. This course complements ECE568, which focuses more on the software aspects of embedded systems. 

Topics Covered:

Weeks Major Topics
1 Introduction to SoCs, technology trends, design challenges
1 Overview of SoC Design Flow & key steps involved (HW/SW partitioning, modeling and co-simulation, communication architecture design, Behavioral synthesis
2 Modeling and co-simulating mixed HW/SW
3 HW/SW partitioning (Designing HW accelerators, interfacing accelerators to software, application-specific instruction processors, custom instruction set generation
3 On-chip communication architecture design (Buses, Networks-on-chip)
3 Behavioral synthesis - generating custom hardware from algorithms (Scheduling, Resource sharing, Advance techniques - loop pipelining, speculative execution, synthesis of pipelined accelerators)
1 Low power SoC design (power estimation and reduction techniques)
1 Current research trends in SoC design

 

Web Address:

https://purdue.brightspace.com

 

Textbooks:

Required:

None

Recommended:

  1. Multiprocessor Systems-on-Chips (Systems on Silicon Series), Ahmed Jerraya and Wayne Wolf, Morgan Kaufmann, 2004
  2. ARM System-on-Chip Architecture, 2 Edition, Steve Furber, Addison-Wesley, 2000
  3. ESL Design and Verification: A Prescription for Electronic System Level Methodology (Systems on Silicon Series), Grant Martin, Brian Bailey, Andrew Piziali, Morgan Kaufmann, 2007
  4. Surviving the SOC Revolution - A Guide to Platform-Based Design, Henry Chang, L.R. Cooke, Merrill Hunt, Grant Martin, Andrew McNelly, Lee Todd, Springer, 1999