ECE 59500 - Semiconductor Manufacturing

Lecture Hours: 3 Credits: 1

This is an experiential learning course.

Counts as:
CMPE Special Content Elective
EE Elective

Experimental Course Offered: Spring 2020

Requisites:
[MA 26200 or MA 26600] and [PHYS 27200 or PHYS 24100] and CHM 11500 and [ECE 59500 Microfabrication Fundamentals or (ECE 59500 MEMS I: Microfabrication and Materials for MEMS)

Requisites by Topic:
Differential equations, introductory physics (mechanics, electricity and magnetism), introductory chemistry.

Catalog Description:
Introduction to manufacturing processes suitable for CMOS and CMOS-compatible integrated devices. Unit processes for multi-level metal interconnects, including physical deposition, plasma enhanced chemical vapor deposition, copper plating, chemical mechanical polishing of dielectrics and metals. Process development of Si/Ge, low-k dielectrics, metal gates, 3D NANDs and photonic devices, etc.

Supplementary Information:
This course will run the last five weeks of the semester.

Required Text(s): None.

Recommended Text(s):
  1. Fabrication Engineering at the Micro- and Nanoscale, 4th Edition, Campbell, Stephen A., Oxford University Press, 2012, ISBN No. 9780199861224.
  2. Introduction to Semiconductor Manufacturing Technology, 2nd Edition, Xiao, Hong, SPIE Press, 2012, ISBN No. 9780819490926.

Learning Outcomes:

A student who successfully fulfills the course requirements will have demonstrated an ability to:
  1. describe major process steps in state-of-the-art CMOS manufacturing. [4,7]
  2. propose a series of processes to address fabrication requirements of CMOS-compatible devices. [1,4,7]

Lecture Outline:

Week Topic
1 Front-end processing for advanced CMOS Silicon-on-insulator substrates, shallow-trench insulation, self-aligned silicide, metal gate, atomic-layer deposition for low-k dielectrics.
2 Back-end processing for copper interconnects Physical vapor deposition, plasma enhanced chemical vapor deposition
3 Damascene process, copper plating, chemical mechanical polishing of dielectrics and metals.
4 Process development and integration. 3D NANDs, through-silicon vias (TSV), silicon photonic devices. Hetero-integration.
5 Packaging, statistical processing control. Exam

Engineering Design Consideration(s):

Economic
Environmental
Global