ECE 49595 - ASIC Fabrication and Test I


In the event that chip fabrication is unavailable, a reconfigurable logic based prototype may be tested instead. The instructor will meet weekly with each design team to monitor progress, explain new concepts, and guide the team in satisfying all course outcomes.

Course Details

Lecture Hours: 1 Lab Hours: 1 Credits: 2

This is an experiential learning course.

Counts as:

Experimental Course Offered:

Fall 2008, Fall 2009, Fall 2010, Fall 2011, Spring 2012


ECE 337

Catalog Description:

The first semester of a two-semester sequence to give teams of 3 to 6 students the experience of designing an ASIC, having the chip fabricated, and testing it. The team of students will develop requirements for a design, prepare the design using VHDL, Verilog, or schematic entry tools, create and use test benches to functionally verify the design, use automated tools to prepare a circuit layout, verify the final layout, submit the layout for fabrication, prepare a physical test bed, test or demonstrate the chip, and document all aspects of the design and test results.

Required Text(s):


Recommended Text(s):

  1. Digital Integrated Circuits , 2nd Edition , Jan M. Rabaey, Anantha Chandrakasan, and Borivoje Nikolic , Prentice -Hall , 2003 , ISBN No. 0130909963
  2. VHDL for Logic Synthesis , 2nd Edition , Andrew Rushton , John Wiley & Sons , 1998 , ISBN No. 047198325x

Learning Outcomes:

A student who successfully fulfills the course requirements will have demonstrated:
  1. Explain critical steps in the preparation of an ASIC design for fabrication and the tools required to perform these steps: functional verification, logic synthesis, physical layout, physical verification, and timing verification. (ALL individually). [k]
  2. an ability to use advanced ASIC design software for at least 2 of the following: functional verification, logic synthesis, physical layout, physical verification, and timing verification. Create or use scripts to automate repetitive aspects of the process. [k]
  3. an ability to define functional and physical requirements for an ASIC design of the team's choosing. [c,e]
  4. an ability to define a circuit architecture that can be expected meet functional requirements subject to performance and area constraints. [c,e]
  5. an ability to estimate speed, throughput, and expected circuit area to ensure that constraints are satisfied.. [c]
  6. an ability to create testbenches and verify the functionality of the design in source code, and after logic synthesis.. [e,k]
  7. an ability to communicate effectively in writing by means of a collective technical report on the project and individual reports on how each outcome was satisfied.. [g]

Lab Outline:

Lab Activity
1-2 Define Design Requirements and Constraints
3-6 Define Chip Architecture
5-10 Prepare design using a hardware description language
8-12 Synthesize design to gate level representation
6-12 Prepare Simulation Test Benches
8-14 Verify functionality of source code and gate level design
12-14 Prepare ASIC Layout. Might not complete until second semester.
13-14 Verify functionality and manufacturability of the layout. Might not complete until second semester.
15 Submit design for Fabrication (if fabrication is available). Might not complete until second semester.

Engineering Design Content:

  • Establishment of Objectives and Criteria
  • Synthesis
  • Analysis
  • Construction
  • Testing
  • Evaluation

Engineering Design Consideration(s):

  • Manufacturability

Assessment Method:

Any completed outcomes (1-7) will be assessed through evaluation of each students outcome completion report (described in outcome 8), corroborated by instructor observation during the semester, and by an end of semester interview. Outcome 8 will be assessed grading of the collective technical report and the individual outcome completion report.