ECE 495G - ASIC Fabrication and Test II


Outcomes 1,2,3 are demonstrated during ASIC Fabrication and Test I. During ASIC Fabrication and Test II, each student must demonstrate outcomes 4,8 and 9. In addition, each student must demonstrate at least one of the outcomes 5,6, and 7. It is possible that some of the outcomes 4 through 8 will have been demonstrated in ASIC Fabrication and Test I. If so, it is not necessary to demonstrate these outcomes again in ASIC Fabrication and Test II.

Course Details

Lab Hours: 2 Credits: 2

This is an experiential learning course.

Counts as:

Experimental Course Offered:

Spring 2008

Catalog Description:

The second semester of a two-semester sequence to give teams of 3 to 6 students the experience of designing an ASIC, having the chip fabricated, and testing it. The team of students will develop requirements for a design, prepare the design using VHDL, Verilog, or schematic entry tools, create and use test benches to functionally verify the design, use automated tools to prepare a circuit layout, verify the final layout, submit the layout for fabrication, prepare a physical test bed, test or demonstrate the chip, and document all aspects of the design and test results. In the event that chip fabrication is unavailable, a reconfigurable logic based prototype may be tested instead. The instructor will meet weekly with each design team to monitor progress, explain new concepts, and guide the team in satisfying all course outcomes.

Required Text(s):


Recommended Text(s):

  1. Digital Integrated Circuits , 2 Edition , Jan M. Rabaey, Anantha Chandrakasan, and Borivoje Nikolic , Prentice-Hall , 2003 , ISBN No. 0-13-090996-3
  2. VHDL for Logic Synthesis , 2 Edition , Andrew Rushton , John Wiley & Sons , 1998 , ISBN No. 0-471-98325-X

Learning Outcomes:

  1. Explain critical steps in the preparation of an ASIC design for fabrication and the tools required to perform these steps: functional verification, logic synthesis, physical layout, physical verification and timing verification. (ALL individually). [None]
  2. Use advanced ASIC design software for: functional verification, logic synthesis, physical layout, physical verification, and timing verification. Create or use scripts to automate repetitive aspects of the process. (Each student must participate in some aspect of this). [None]
  3. Define functional and physical requirements for an ASIC design of the team's choosing. (Each student must participate in some aspect of this). [None]
  4. Define a circuit architecture that can be expected meet functional requirements subject to performance and area constraints. (Each student must participate in some aspect of this). [None]
  5. Estimate speed, throughput, and expected circuit area to ensure that constraints are satisfied. (At least one student). [None]
  6. Create testbenches and verify the functionality of the design in source code, after logic synthesis, and after layout. (at least one student). [None]
  7. Create an ASIC layout that is verified and ready for fabrication. (At least one student). [None]
  8. Design, implement, and use a hardware testbed for verification of the chip after fabrication. If fabrication is not available, create a reconfigurable logic prototype for testing. Off-the-shelf components my be used. The testbed should verify functionality and performance. (Each student must participate in some aspect of this). [None]
  9. Communicate effectively in writing by means of a collective technical report on the project and individual reports on how each outcome was satisfied. (Each student must participate in this for both semesters). [None]

Engineering Design Content:

  • Synthesis
  • Analysis
  • Testing

Engineering Design Consideration(s):

  • Economic
  • Manufacturability

Assessment Method:

Any completed outcomes (1-7) will be assessed through evaluation of each student's outcome completion report (described in outcome 8), corroborated by instructor observation during the semester, and by an end of semester interview. Outcome 8 will be assessed grading of the collective technical report and the individual outcome completion report.