ECE 33700 - ASIC Design LaboratoryLecture Hours: 1 Lab Hours: 3 Credits: 2
EE Elecive - Adv Level Lab
Normally Offered: Each Fall, Spring
ECE 27000 Minimum Grade of C
Introduction to standard cell design of VLSI digital circuits using VHDL hardware description language. Emphasis on how to write VHDL that will map readily to hardware. Laboratory experiments using commercial grade computer-aided design (CAD) tools for VHDL based design, schematic based logic entry, logic and VHDL simulation, automatic placement and routing, timing analysis and testing.
Formerly offered as ECE 495D - Spring 2002 through Fall 2005.
Required Text(s): None.
Recommended Text(s): None.
|1||Course overview, HDL synthesis and simulation design flow|
|2||Combinational logic design - schematic and HDL|
|3||Use of test benches, timing constraints, optimization trade-offs|
|4||Sequential logic functions, HDL based state machine design|
Engineering Design Content:
Engineering Design Consideration(s):