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ECE 33700 - ASIC Design Laboratory

Lecture Hours: 1 Lab Hours: 3 Credits: 2

Professional Attributes
Upper Level Lab

Normally Offered: Each Fall, Spring

ECE 27000 Minimum Grade of C

Catalog Description:
Introduction to standard cell design of VLSI digital circuits using VHDL hardware description language. Emphasis on how to write VHDL that will map readily to hardware. Laboratory experiments using commercial grade computer-aided design (CAD) tools for VHDL based design, schematic based logic entry, logic and VHDL simulation, automatic placement and routing, timing analysis and testing.

Supplementary Information:
Formerly offered as ECE 495D - Spring 2002 through Fall 2005.

Required Text(s): None.

Recommended Text(s): None.

Assessment Method for Learning Objectives: Outcomes x through xv will be demonstrated by means of a final design project to be completed by teams of two or three students. Final projects will be evaluated on a per team basis, but individual participation will also be evaluated.

Lab Outline:

Week(s) Activity
1 Course overview, HDL synthesis and simulation design flow
2 Combinational logic design - schematic and HDL
3 Use of test benches, timing constraints, optimization trade-offs
4 Sequential logic functions, HDL based state machine design

Engineering Design Content:

Establishment of Objectives and Criteria

Engineering Design Consideration(s):