ECE 43700 - Computer Design and Prototyping

Note:

This course is a required CMPE Advanced Elective for catalog terms prior to Fall 2018. For Fall 2018 and later catalog terms it is a CMPE Selective.

Course Details

Lecture Hours: 3 Lab Hours: 3 Credits: 4

Counts as:

  • EE Adv Level Lab
  • CMPE Selective

Normally Offered:

Each Fall

Campus/Online:

On-campus only

Requisites:

ECE 33700 and ECE 36200

Catalog Description:

Computer design is the science and art of selecting and interconnecting hardware components to build a computer that meets functional, performance, and cost goals. In this course, students will learn to design a uniprocessor computer system, including processor datapath, processor control, memory systems, and I/O. The course provides a thorough and detailed treatment of basic computer arithmetic algorithms, multi-cycle implementations of modern computer instruction sets, pipelined CPU designs, design of cache hierarchy and virtual memory, and fundamentals of computer system I/O. The course also includes evaluation and analysis of processor and memory performance. A project which involves the design and implementation of multi-cycle CPU, and a pipelined CPU with a cache hierarchy using CAD tools is an integral part of the course.

Required Text(s):

  1. Computer Organization and Design: RISC-V Edition , 2nd Edition , J. L. Hennessy and D. A. Patterson , Morgan Kaufmann Publisher , 2020 , ISBN No. 978-0128203316

Recommended Text(s):

Learning Outcomes:

A student who successfully fulfills the course requirements will have demonstrated:
  1. an understanding of basic computer arithmetic algorithms. [1,2]
  2. an ability to understand and implement single-cycle implementations of a computer instruction set. [1,2]
  3. an ability to understand and design a pipelined CPU, and cache hierarchy including virtual memory. [1,2]
  4. an understanding of the fundamentals of computer system I/O. [1,2]
  5. an ability to analyze and evaluate CPU and memory hierarchy performance. [1,6]
  6. experience with the design, simulation, and documentation of a single-cycle CPU, and a pipelined CPU with a cache . [1,2,3,6,7]

Lecture Outline:

Week Topic
1 Introduction, Performance
2 Cont., Instructions
3 Arithmetic
4 Cont., Datapath
5 Cont., Control
6 Cont.
7 Cont.
8 Pipelining
9 Cont.
10 Memory Hierarchies
11 Cont.
12 Cont.
13 More Arithmetic
14 Cont., I/O
15 Cont.
Final Final exam

Lab Outline:

Week Lab Exercises
1-2 VHDL/FPGA Review
3-10 Basic CPU Design, Simulation, and Prototyping
11-15 Extended CPU Design, Simulation, and Prototyping

Assessment Method:

none