ECE 33700 - ASIC Design Laboratory


This course is an CMPE Core Course for catalog terms prior to Fall 2018. For Fall 2018 and later catalog terms it is a CMPE Selective.

Course Details

Lecture Hours: 1 Lab Hours: 3 Credits: 2

Counts as:

  • EE Adv Level Lab
  • CMPE Selective

Normally Offered:

Each Fall, Spring


On-campus only


ECE 27000 Minimum Grade of C

Catalog Description:

Introduction to standard cell design of Application Specific Integrated Circuits (ASICs) using modern hardware description languages (HDLs). Emphasis on how to write HDL code that will map readily to hardware. Laboratory experiments using commercial grade computer-aided design (CAD) tools for HDL based design, logic simulation, automatic placement and routing, timing analysis and verification.

Required Text(s):

  1. Digital Integrated Circuit Using Verilog and SystemVerilog , 1st Edition , Ronald Mehler (Electronic access through Purdue Libraries) , Newnes , 2015 , ISBN No. 978-0124080591
  2. I-Clicker

Recommended Text(s):

  1. Digital Design: Principles and Practices , John Wakerly (Any edition after the 2nd edition is sufficient)

Learning Outcomes:

A student who successfully fulfills the course requirements will have demonstrated an ability to:
  1. design combinational and sequential logic in a variety of styles: schematic, structural, behavioral, and dataflow. Demonstrate an awareness of timing and resource usage associate with each approach. [1,2]
  2. use, modify, and create scripts to control the logic synthesis process. [1,2]
  3. create a test bench and use it to verify a design that incorporates multiple sequential blocks. [1,6]
  4. place, route, and verify timing of an ASIC design. [None]
  5. determine the RTL level architecture implied by HDL code of moderate complexity. [1]
  6. explain the difference between various ASIC and digital system design approaches -- standard cell, full custom, and programmable devices. [2,4]
  7. demonstrate an awareness of timing and resource usage associated with each logic design approach. [1,2]

Lecture Outline:

Week(s) Lecture Topics
1-2 Register Transfer Level (RTL) design of systems
3-4 Review of System Verilog syntax
5-7 Finite State machine (FSM) review, system control using FSM
8 SoC bus protocols
9 Alternatives to ASIC design, programmable logic implementation technologies
10-11 Static timing analysis
12-13 Analyze hardware architecture of existing System Verilog code
14 Final design demonstration

Lab Outline:

Lab Activity
1 HDL synthesis and simulation design flow
2 Combinational logic design, coding styles, exhaustive test vectors
3 Lotic synthesis constraints, Assertions, directed test vectors, coverage
4 Sequential logic functions, HDL based state machine design, sequential tests
5-9 Subsystem designs: UART, FSM controlled computation, SoC bus protocols
10-11 IC layout and timing analysis
12-15 small team design assignment

Engineering Design Content:

  • Synthesis
  • Analysis
  • Testing
  • Evaluation

Engineering Design Consideration(s):

  • Manufacturability

Assessment Method:

Exams, Quizzes and Lab demonstrations and design submissions