ECE 33700 - ASIC Design Laboratory

Lecture Hours: 1 Lab Hours: 3 Credits: 2

Counts as:
CMPE Selective
EE Elective - Adv Level Lab

Normally Offered: Each Fall, Spring

ECE 27000 Minimum Grade of C

Catalog Description:
Introduction to standard cell design of Application Specific Integrated Circuits (ASICs) using modern hardware description languages (HDLs). Emphasis on how to write HDL code that will map readily to hardware. Laboratory experiments using commercial grade computer-aided design (CAD) tools for HDL based design, logic simulation, automatic placement and routing, timing analysis and verification.

Supplementary Information:
This course is an CMPE Core Course for catalog terms prior to Fall 2018. For Fall 2018 and later catalog terms it is a CMPE Selective.

Required Text(s):
  1. I-Clicker.
  2. Verilog for Digital Design, Frank Vahid, Roman Lysecky, John Wiley & Sons, 2007, ISBN No. 9780470052624.
Recommended Text(s):
  1. Digital Design Principles and Practices, 4th Edition, John F. Wakerly, Pearson Prentice Hall, 2005, ISBN No. 0131863894.

Learning Outcomes:

A student who successfully fulfills the course requirements will have demonstrated an ability to:
  1. design combinational and sequential logic in a variety of styles: schematic, structural, behavioral, and dataflow. Demonstrate an awareness of timing and resource usage associate with each approach. [1,2]
  2. use, modify, and create scripts to control the logic synthesis process. [1,2]
  3. create a test bench and use it to verify a design that incorporates multiple sequential blocks. [1,6]
  4. place, route, and verify timing of an ASIC design. [None]
  5. determine the RTL level architecture implied by HDL code of moderate complexity. [1]
  6. explain the difference between various ASIC and digital system design approaches -- standard cell, full custom, and programmable devices. [2,4]
  7. demonstrate an awareness of timing and resource usage associated with each logic design approach. [1,2]

Lecture Outline:

Week(s) Lecture Topics
1-2 Combinational logic design
3-4 Sequential logic design
5-8 Register Transfer Level (RTL) design of systems
9 Alternatives to ASIC design, programmable logic implementation technologies
10-13 No lecture
14 Preparation for final presentations and demonstrations

Lab Outline:

Lab Activity
1 Course overview, HDL synthesis and simulation design flow
2 Combinational logic design - schematic and HDL
3 Use of test benches, timing constraints, optimization trade-offs
4 Sequential logic functions, HDL based state machine design
4-7 System level design, writing ASIC specifications
9-15 Final project
15 Student presentations and final reports

Engineering Design Content:

Establishment of Objectives and Criteria

Engineering Design Consideration(s):