ECE 59500 - Semiconductor Device Integration Through Simulation

Course Details

Lecture Hours: 3 Credits: 3

Counts as:

  • EE Elective
  • CMPE Selective - Special Content

Normally Offered:

Each Fall


On-campus and online


ECE 59500 Integrated Circuit/MEMS Fabrication Laboratory, or ECE 59500 Semiconductor Fundamentals plus ECE 59500 Semiconductor Manufacturing; ECE 30500, ECE 60600, or ECE 61200

Requisites by Topic:

Introductory understanding of semiconductor manufacturing unit processes and integration, and of MOS transistor operation and scaling; introductory Linux

Catalog Description:

This course will use semiconductor Technology-Computer-Aided-Design (TCAD) tools to present methods of integration of semiconductor process modules into modern CMOS devices. Commercial TCAD tools will be used by the students both to simulate device manufacturing flows and to simulate device characteristics. The objectives are both to teach the capabilities, limitations, and calibration of such commercial simulation tools, and to demonstrate their use in developing and optimizing manufacturing flows for complex modern semiconductor devices. The course will begin with the final nodes of planar MOS transistors (32nm), and proceed through FinFETs and Gate- All-Around (GAA) transistors. Process performance "boosters" such as strain engineering and high-K gate stack development will be presented and integrated into devices, along with scaling methods such as self-alignment for both device and interconnect structures. Integrated power delivery through buried power rails and back-side vias will also be presented. The ways in which non-planar (FinFET, GAA) devices surpass the limitations of planar device scaling through structural advantages in channel potential control will be explained and demonstrated through simulation, along with the adaptation of the integration methods developed for planar devices to optimize non-planar transistor structures. In order to simulate quantum effects in nanoscale devices, commercial TCAD tools have recently incorporated atomistic simulation - such atomistic simulation for highly scaled devices will be presented and compared to conventional TCAD transport simulation.

Required Text(s):


Recommended Text(s):

  1. Integrated Circuit Fabrication , James D Plummer, Peter Griffin , Cambridge University Press , 2023 , ISBN No. 9781009303583

Learning Outcomes:

A student who successfully fulfills the course requirements will have demonstrated an ability to:
  1. Explain the limits of planar MOSFET scaling, and the fabrication techniques developed for the ultimate planar device generations. [1,2,6,7]
  2. Explain the scaling advantages of modern non-planar structures, and the integration methods that can be used to create such non-planar devices.. [1,2,6,7]
  3. Use representative commercial TCAD software tools to create and optimize semiconductor fabrication flows and to simulate device performance, including introduction to the use of atomistic simulation to capture quantum device effects. [1,5,6,7]

Lecture Outline:

Week Major Topics
1 Overview of present state of the art in semiconductor manufacturing; introduction to nanohub and the Silvaco Victory Process and Victory Device simulation tools
2 Geometrical versus physics-based structure definition; grid construction and effects; progressive "continuum" models; simulation calibration and incremental prediction
3 Review of semiconductor unit processes: cleaning, oxidation, doping, implantation, etching, planarization, deposition, back-end processes and wafer bonding
4 Lithography resolution enhancement techniques; immersion DUV and EUV; resolution versus depth-of-field, numerical aperture; registration; hardmasks; multipatterning, LELE, SADP, SAQP, cut masks
5 Review of MOSFET gate electrostatics and channel engineering; scaling limiters in planar MOSFETs; DIBL, GIDL, Reliability Limits, Random Doping Fluctuation
6 Shallow Trench Isolation; Self-aligned Silicides and Ultra-Shallow Junctions, Self-Aligned Contacts, Contact-over-Active-Gate
7 Strain engineering for mobility enhancement
8 High-K gate insulators and replacement metal gate; Integration options; high-K-last replacement gate integration
9 32nm MOSFET device flow in simulation: physical simulation and simulation of electrical device characteristics
10 FinFET electrostatics; geometric construction of FinFET for electrical comparison with scaled planar MOSFET; FinFET parasitics
11 FinFET integration; Silicon etch, recessed STI, epitaxial overgrowth for S/D, diffusion breaks, MEOL with CoAG
12 GAA electrostatics; geometric construction of GAA FET for electrical characterization
13 GAA integration: epitaxy and etch requirements; side-spacers and parasitic channels
14 Wafer-to-wafer and die-to-wafer hybrid bonding; face-to-face and face-to-back bonding; buried power rails and through-silicon-vias
15 Thermal effects in non-planar devices; thermal effects in thinned silicon
16 Process optimization: selection of geometry based on process capability and electrical/stress/thermal impact of geometry; layout rule restrictions imposed by patterning constraints; DTCO / STCO

Assessment Method:

Homework, projects, and exams (4/2024)