Integration Through Simulation

Learning Objective:

• Integrate semiconductor fabrication unit processes into manufacturing flows capable of delivering complex physical device structures
• Describe the limits of planar MOSFET scaling, and the fabrication techniques developed for the ultimate planar device generations
• Explain the scaling advantages of modern non-planar structures, and the integration methods that can be used to create such non-planar devices
• Apply commercial TCAD software tools to create and optimize semiconductor fabrication flows and to simulate device performance

Description:

This course will use semiconductor Technology-Computer-Aided-Design (TCAD) tools to present methods of integration of semiconductor process modules into modern CMOS devices. Commercial TCAD tools will be used by the students both to simulate device manufacturing flows and to simulate device characteristics, with objectives both to teach the capabilities, limitations, and calibration of such commercial simulation tools, and to demonstrate their use in developing and optimizing manufacturing flows for complex modern semiconductor devices. The course will begin with the final nodes of planar MOS transistors (32nm), and proceed through FinFETs and Gate-All-Around (GAA) transistors. Process performance "boosters" such as strain engineering and high-K gate stack development will be presented and integrated into devices, along with scaling methods such as self-alignment for both device and interconnect structures. Integrated power delivery through buried power rails and back-side vias will also be presented. In addition to training for semiconductor process and device engineers, the course should provide students pursuing fabless circuit design research or employment with background to refine intuition with respect to layout and design of analog and digital circuits in modern VLSI processes.

Topics Covered:

• Overview of present state of the art in semiconductor manufacturing
• Geometrical versus physics-based structure definition; grid construction and effects; progressive "continuum" models; simulation calibration and incremental prediction
• Review of semiconductor unit processes: cleaning, oxidation, doping, implantation, etching, planarization, deposition, back-end processes and wafer bonding
• Lithography resolution enhancement techniques; immersion DUV and EUV; resolution versus depth-of-field, numerical aperture; registration; hardmasks; multipatterning; LELE, SADP, SAQP, cut masks
• Review of MOSFET gate electrostatics and channel engineering; scaling limiters in planar MOSFETs; DIBL, GIDL, Reliability Limits, Random Doping Fluctuation
• Shallow Trench Isolation; Self-aligned Silicides and Ultra-Shallow Junctions, Self-Aligned Contacts, Contact-over-Active-Gate
• Strain engineering for mobility enhancement
• High-K gate insulators and replacement metal gate; Integration options; high-K-last replacement gate integration
• 32nm MOSFET device flow in simulation: physical simulation and simulation of electrical device characteristics
• FinFET electrostatics; geometric construction of FinFET for electrical comparison with scaled planar MOSFET; FinFET parasitics
• FinFET integration; Silicon etch, recessed STI, epitaxial overgrowth for S/D, diffusion breaks, MEOL with CoAG
• GAA electrostatics; geometric construction of GAA FET for electrical characterization
• GAA integration: epitaxy and etch requirements; side-spacers and parasitic channels
• Wafer-to-wafer and die-to-wafer hybrid bonding; face-to-face and face-to-back bonding; buried power rails and through-silicon-vias
• Thermal effects in non-planar devices; thermal effects in thinned silicon
• Process optimization: selection of geometry based on process capability and electrical/stress/thermal impact of geometry; layout rule restrictions imposed by patterning constraints; DTCO/STCO

Prerequisites:

Students need to have some prior exposure to semiconductor fabrication unit processes (lithography, etch, deposition, doping, planarization, etc) - semiconductor unit processes will be reviewed briefly, but not covered in detail. Similarly, students need basic understanding of CMOS transistor operation and scaling.

Applied / Theory:

90/10

Web Address:

https://purdue.brightspace.com

Homework:

In addition to conventional problem sets, students will be expected to modify and create TCAD code to simulate physical device structures and their resultant electrical characteristics. The course will also draw upon a variety of research publications describing the advent of different device features and implementation methods during the historical evolution of semiconductor design. Students will be asked to locate, read, and extract information from such research publications.

Exams:

Exams will be online

Textbooks:

Reference:

Integrated Circuit Fabrication, Science and Technology, James D Plummer, Peter Griffin, Cambridge University Press, 2023, ISBN 9781009303606 (eTextbook), 9781009303583 (Hardcover)

Note: this is a new publication, I believe not yet available through Purdue Library; I will request the library to obtain it; this text is of particular significance as a reference for the semiconductor unit process familiarity that is otherwise a prerequisite for this course.

Computer Requirements:

A laptop or desktop computer with monitor is essential to adequately display the visual simulated TCAD output (a phone is not sufficient). The computation software will reside and execute on remote computer networks at Purdue, rather than on student-supplied systems