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Architecting Components for a 10 Billion Transistor Processor

Event Date: March 24, 2015
Speaker: Reetuparna Das
Speaker Affiliation: University of Michigan
Time: 10:30am
Location: EE 317
Contact Name: Professor Yung-Hsiang Lu
Contact Phone: 765-49-42668
Contact Email: yunglu@purdue.edu

Abstract
Soon we may have processors with over ten billion transistors organized into hundreds of cores delivering supercomputer-like teraflops performance. To unlock this performance potential, however, we need dramatic improvements in processor efficiency to stay within the strict power budget. A significant source of inefficiency in today's general-purpose processors is that they tend to expend equal resources to varied applications without accounting for their individual needs. In this talk, I will present two solutions to address such inefficiency in both core and un-core parts of the processor. Composite cores eliminate needless power expended by out-of-order cores for applications with little or easy to exploit instruction-level parallelism. Aergia on-chip network prioritizes packets of network-sensitive applications to attain significantly higher throughput. I will also briefly discuss our on-going research that seeks to move compute close to storage in order to attain orders of magnitude improvement in efficiency for Big Data applications.

Biography
Reetuparna Das is a research faculty in the EECS Department at the University of Michigan. She is also the researcher-in-residence for the Center for Future Architectures Research (CFAR). Prior to this, she was a Research Scientist at Intel Labs in Santa Clara. Her research interests include computer architecture, and its interaction with software systems and VLSI technologies. Her most notable contributions include the design of application-aware and energy proportional on-chip interconnects for Kilo-core processors and fine-grained heterogeneous core architectures. She has received several awards including an IEEE Top Picks award, outstanding research assistant and outstanding teaching assistant awards from the CSE department at Pennsylvania State University. She has authored over 30 articles in peer reviewed journals and conferences. She has a Ph.D. in Computer Science and Engineering from the Pennsylvania State University, University Park.