Purdue’s project — CHEETA: CMOS+MRAM Hardware for Energy-EfficienT AI — will adopt a CMOS+X approach, specifically leveraging the unique capabilities of magnetic random-access memory (MRAM) to design efficient in-memory computing hardware fabrics. This project will pursue lab-to-fab transition of pioneering research performed at Purdue for over a decade. The project brings together a strong team from academia, industry and national labs with diverse strengths in semiconductors and microelectronics that span materials, devices, circuits, architecture and systems.

 

The project was one of four announced Sept. 18 that received funding from the Applied Research Institute. SCMC, which is led by ARI, is one of eight national hubs led by ARI and comprising an innovation ecosystem of diverse partners driven to accelerate expansion of America’s microelectronics base.

 

“This win once again underscores Purdue’s national leadership in microelectronics and semiconductors, from our world-leading research and industry partnership to transformational investments in infrastructure and pioneering education and workforce development programs,” Purdue President Mung Chiang said. “Purdue is strongly committed to supporting the CHIPS Act and the U.S. DOD’s ME Commons program, enhancing economic prosperity to the Silicon Heartland and national security of the U.S.”

 

The Purdue-led team includes the following faculty from the Elmore Family School of Electrical and Computer Engineering: Kaushik Roy, the Edward G. Tiedemann, Jr. Distinguished Professor of ECE; Anand Raghunathan, the Silicon Valley Professor of ECE; and Sumeet Gupta, Elmore Associate Professor of ECE, with collaborating partners Everspin Technologies, Georgia Institute of Technology, Naval Surface Warfare Center Crane Division, Argonne National Laboratory, University of Michigan and Northrop Grumman. The project will receive $21 million over four years.

 

“By uniting the strengths of our partnerships with Argonne National labs, NSWC Crane as well as government agencies, leading industry partners and top academic institutions, we are embarking on a groundbreaking project that will push the boundaries of semiconductor innovation,” said Karen Plaut, Purdue’s executive vice president for research. “The outcomes of this collaboration will not only enhance the performance and resilience of defense technologies but also solidify our leadership in advancing critical technologies that protect our nation and shape the future of defense.”

 

Roy’s work is affiliated with the university’s Institute of Chips and AI, a College of Engineering institute focusing on AI and semiconductors, as well as the Institute for Physical AI — key focus areas of the Purdue Computes initiative. Purdue Computes emphasizes the university’s extensive technological and computational environment.

 

The CHEETA project aims to deliver impactful improvements in energy efficiency and sensor-to-decision latency compared to the current commercial standard. These capabilities are expected to benefit defense applications by providing highly efficient AI hardware solutions with significant advancements in the “size, weight and power” (SWaP) metrics.

 

“The CHEETA project represents a game-changing leap in microelectronics, blending CMOS and MRAM technologies to tackle the critical challenges of energy efficiency and latency in AI hardware,” Roy said. “Our collaboration in the CHEETA initiative underscores our commitment to advancing MRAM technology and integrating it with cutting-edge CMOS processes, paving the way for transformative improvements in AI system performance and efficiency.”