Challenges in Architecting System-on-Chips

Event Date: April 16, 2024
Location: 11:15 am
Contact Name: MSEE 112
Priority: No
School or Program: Electrical and Computer Engineering
College Calendar: Hide
Pramod Govindan
Rambus Chip Technologies


This presentation discusses some of the challenges involved in architecting System on Chips. A brief introduction to SoC is provided in the beginning. Furthermore, a sample SoC architecture is discussed with some of the key modules and interfaces highlighted. The presentation discusses various topics such as Pad multiplexing, Multiple Clocks, Internal Buses, Memory Sub system, Mixed Signal, Debug Facilities, IP block integration, Low Power design, Verification phases etc. along with the challenges faced by the architects/designers when these are being incorporated in an SoC. The presentation utilizes analogies to explain some of the concepts.


Dr. Pramod Govindan received his Bachelor of Technology in electronics and communication engineering from Government Engineering College in India, a Master of Science in VLSI and microelectronics and a Doctor of Philosophy in electrical engineering from the Illinois Institute of Technology (IIT), Chicago. He had held technical/managerial positions at Analog Devices Inc. (ADI), California, and Rambus Chip technologies (India), and served as Assistant Professor at the University of North Florida (UNF), and Teaching Faculty at Oregon Institute of Technology (OIT) and University of Maryland (UMD). His research interest and effort primarily include reconfigurable hardware system-on-chip based digital system design and hardware realizations of Cryptographic algorithms on application specific integrated circuits (ASIC) and field programmable gate arrays (FPGA).


Professor David Janes,

2024-04-16 08:00:00 2024-04-16 17:00:00 America/Indiana/Indianapolis Challenges in Architecting System-on-Chips Pramod Govindan Rambus Chip Technologies 11:15 am