ECE 33700 - ASIC Design Laboratory
Note:
This course is an CMPE Core Course for catalog terms prior to Fall 2018. For Fall 2018 and later catalog terms it is a CMPE Selective.
Course Details
Lecture Hours: 1 Lab Hours: 3 Credits: 2
Counts as:
- EE Adv Level Lab
- CMPE Selective
Normally Offered:
Each Fall, Spring
Campus/Online:
On-campus only
Requisites:
ECE 27000 Minimum Grade of C
Catalog Description:
Introduction to standard cell design of Application Specific Integrated Circuits (ASICs) using modern hardware description languages (HDLs). Emphasis on how to write HDL code that will map readily to hardware. Laboratory experiments using commercial grade computer-aided design (CAD) tools for HDL based design, logic simulation, automatic placement and routing, timing analysis and verification.
Required Text(s):
- Digital Integrated Circuit Using Verilog and SystemVerilog , 1st Edition , Ronald Mehler (Electronic access through Purdue Libraries) , Newnes , 2015 , ISBN No. 978-0124080591
- I-Clicker
Recommended Text(s):
- Digital Design: Principles and Practices , John Wakerly (Any edition after the 2nd edition is sufficient)
Lecture Outline:
| Week(s) | Lecture Topics |
|---|---|
| 1-2 | Register Transfer Level (RTL) design of systems |
| 3-4 | Review of System Verilog syntax |
| 5-7 | Finite State machine (FSM) review, system control using FSM |
| 8 | SoC bus protocols |
| 9 | Alternatives to ASIC design, programmable logic implementation technologies |
| 10-11 | Static timing analysis |
| 12-13 | Analyze hardware architecture of existing System Verilog code |
| 14 | Final design demonstration |
Lab Outline:
| Lab | Activity |
|---|---|
| 1 | HDL synthesis and simulation design flow |
| 2 | Combinational logic design, coding styles, exhaustive test vectors |
| 3 | Lotic synthesis constraints, Assertions, directed test vectors, coverage |
| 4 | Sequential logic functions, HDL based state machine design, sequential tests |
| 5-9 | Subsystem designs: UART, FSM controlled computation, SoC bus protocols |
| 10-11 | IC layout and timing analysis |
| 12-15 | small team design assignment |
Assessment Method:
Exams, Quizzes and Lab demonstrations and design submissions