Peide Ye

Purdue University researchers have demonstrated a new way to build computer chips vertically, stacking multiple layers of transistors, logic and memory on a full-size 200-millimeter silicon wafer. The approach could help future chips pack more computing power into less space while reducing the energy needed to move data.

The work, led by Peide D. Ye, the Richard J. and Mary Jo Schwartz Professor in Purdue’s Elmore Family School of Electrical and Computer Engineering, in close collaborations with Haitong Li, assistant professor in the same School of Electrical and Computer Engineering and Haiyan Wang, the Basil S. Turner Professor of Engineering, is published in Nature Nanotechnology.

The team demonstrated three vertically integrated layers of indium oxide-based transistors on a 200-millimeter, or roughly 8-inch, silicon wafer. The devices showed strong performance and consistency across the wafer.

Modern chips are largely built in two dimensions, with transistors arranged side by side. As engineers continue to shrink those devices, it becomes increasingly difficult to gain performance simply by making them smaller. Monolithic 3D integration offers another option by building functional layers directly on top of one another.

“This work shows that we can move beyond simply making transistors smaller and begin building upward in a practical, wafer-scale way,” Ye said. “By stacking high-performance logic and memory directly on top of one another and on top of Si CMOS platform, we can increase functionality in the same footprint and open new possibilities for faster, more energy-efficient computing.”

One challenge is ensuring that adding new layers does not damage the electronics already beneath them. Many semiconductor materials require high temperatures during fabrication. The Purdue team instead used extremely thin layers of indium oxide deposited via a relatively low-temperature process compatible with later stages of conventional chip manufacturing.

The researchers fabricated three types of transistors in separate tiers, including devices capable of nonvolatile memory that retain information even when power is removed. Tests showed that devices on upper layers did not degrade the performance of those below, suggesting additional layers could eventually be added.

The team also connected devices across the layers to create working logic and memory circuits, including inverters, ferroelectric nonvolatile memory and embedded dynamic random-access memory.

To explore the technology’s potential for artificial intelligence, the researchers designed a four-tier computing-in-memory accelerator for large language models. Computing-in-memory places computation closer to where data is stored, reducing the time and energy spent moving information back and forth.

In simulations using AI workloads including BERT and GPT-2, the 3D architecture achieved speedups of 1.4 to 2.9 times compared with a comparable two-dimensional design.

The scale of the demonstration is also important. The team fabricated more than 100,000 devices across 52 dies on the 200-millimeter wafer, helping demonstrate the uniformity needed for future large-scale manufacturing.

Purdue researchers Chang Niu and Linjia Long contributed equally to the work. The research involved collaborators from Purdue ECE, the Birck Nanotechnology Center and the School of Materials Engineering.