Advances in modern manufacturing and integration technologies have enabled rapid progress in advanced packaging in the past decade, ushering in a new era of SysMoore designs characterized by higher density and increased performance and data bandwidth. The next decade promises to be the time for the design automation (EDA) industry to give wings to engineering teams across the industry – foundry, OSAT, chip and 3D IC system designers of the SysMoore era, to accelerate the technological and scalability gains and drive the next wave of transformative products.

 

Ensuring time-zero manufacturing quality, high yield and life-time reliability and safety of designs is key to realizing these next-generation of innovative products powering trillions of connecting devices of future. This requires comprehensive design verification solutions for the system-of-chips and chiplets, coupled with holistic design and manufacturing enablement methodology. In this talk, we will provide insights into some of the myriad manufacturing, quality and productivity challenges faced by 3D IC design teams; and discuss the state of the art in die-to-die IP and end-to-end design automation to address them. We will discuss how innovations in 3D design-for-test/manufacturing/reliability (DFx), silicon-lifecycle-management (SLM) and yield analysis are paving the way for higher quality and more productive SysMoore era heterogenous integration and disaggregation designs.

 

If time allows, he would love to share his thoughts and answering questions, on developing a career path in semiconductors, and how to balance learning and growth, between technology and business, as well as startup and corporate.