System Cache Architect and Design Engineer

 

Location: San Diego USA

Full time

Job requisition id 3040423

 

Company: Qualcomm Technologies, Inc.

Job Area: Engineering Group, Engineering Group > Hardware Engineering

 

General Summary:

The SoC memory team group consists of a multi-disciplinary group involved from early product specification and analysis effort to final RTL delivery of high-performance memory systems to the SoCs. A key function of the job is to identify architecture bottlenecks and drive micro-architecture choices using performance and power analysis feedback.

 

Candidates should have strong knowledge of memory systems, caching, PPA tradeoffs, RTL design, ASIC flows, synthesis tools, process nodes, VLSI design, and successful industry experience with deployment of IPs in large SoC projects while working in a collaborative environment.

 

Minimum Qualifications:

 

Skills/Experience:

Responsibilities:

The successful applicant will be responsible for creating architecture, micro-architecture specifications as well as analyzing the performance results, collaborate with modeling teams to evaluate architectural tradeoffs, and ensure successful implementation of architectural features.

 

Responsibilities also include evaluating new IPs, driving new memory technology deployments as well as defining system wide guidelines for IPs to inter-operate together with the memory system in the SoC.

 

Candidate should also be able to deliver RTL, support verification and silicon validation teams, and work with SW teams to support successful deployments of the memory system.

 

Keywords: Computer Architecture, Memory Systems, Caches, DRAM, SRAM

 

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