January 26, 2021

Qualcomm full-time and internship opening (low power design)

Position Type: Research
Priority: No
Degree Requirement: MS
Qualcomm full-time and internship opening (low power design)
 
I am from Qualcomm (Purdue MSECE alumni, 2000) and my team has a full-time opening for master new graduate (2021/5) and also internship opening for summer 2021.  Job details here and below. 
 
Jason Hu
Senior Director of Technology
Qualcomm Inc.
408-718-5148 (cell)
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Company: Qualcomm Technologies, Inc.
Location: San Diego, CA
Job Area: Engineering Group, Engineering Group > ASICS Engineering
Full-time
 
Job Overview:
Qualcomm is a company of inventors that unlocked 5G ushering in an age of rapid acceleration in connectivity and new possibilities that will transform industries, create jobs, and enrich lives. But this is just the beginning. It takes inventive minds with diverse skills, backgrounds, and cultures to transform 5Gs potential into world-changing technologies and products. This is the Invention Age - and this is where you come in.
  • Design adaptive power management controller, on-chip sensor controller and digital power meter.
  • Perform RTL design, simulation, synthesis, timing analysis, lint check, clock domain crossing check, conformal low power check, and formal verification for IP blocks.
  • Work closely with technology/circuit design team to close IP block specification/requirement.
  • Work closely with verification/physical design team to complete the IP design implementation.
  • Support SoC team to integrate low power / power management IP solution into wireless SoC chips and front-end design flows.
  • Work closely with system/software/test team to enable the low power feature in wireless SoC product.
  • Work closely with system/software/test team to enable functional safety feature in automotive SoC product.
  • Create/Enhance low power methodologies covering entire design cycle from RTL to GDS. Analyze how a new methodology will affect different phases of the design/verification cycle and work on fixing any issues.
  • Provide feedback for low-power chip and system architecture.
  • Understand and perform block & chip-level power analysis.
  • Understand and create block-level power models.
Minimum Qualifications
  • Bachelor's degree in Science, Engineering, or related field.
  • 5+ years ASIC design, verification, or related work experience.
Preferred Qualifications
  • Masters or PhD in Electrical or Computer Engineering
  • Familiar with ASIC front-end design process and related flow, including u-arch, RTL coding, simulation, synthesis, STA.
  • Understanding of electrical engineering concepts, circuit analysis and logic design skills.
  • Previous experience in AVS (adaptive voltage scaling) desired.
  • Familiarity with advanced low power techniques and tools such as UPF, CLP, power aware DV and high speed clocking desired.
  • Proficiency in Verilog/System Verilog coding, verification techniques, and scripting language, such as: Perl, Python, Tcl, and Make etc.
  • Good understanding of SoC architecture/micro-architecture.
  • Understanding of automotive functional safety standard ISO 26262 and analysis technique (FMEA/FMEDA) is a plus.
  • Strong debugging capabilities at simulation, emulation, and Silicon environments, including ability to design interesting debug experiments.
  • Collaborate closely with cross-function team to research, design and implement performance and power management strategy for product roadmap.