Abhijeet Paul

Performance Analysis of SiGe/Si core/shell NWFETs

Performance analysis of SiGe/Si core/shell NWFETs Abhijeet Paul, Saumitra Mehrotra, Mathieu Luisier and Gerhard Klimeck


  • Performance assessment of SiGe nanowire FETs(NWFETs), ultra-scaledregime, next-gen CMOS solution.


  • Bandstructure: Virtual Crystal Approximation in TB (TB-VCA).
  • Transport: Ballistic Virtual Source model.
  • Performance metrics: Vinj,ION and intrinsic gate delay (tdelay).


  • n/p-FETs better for higher Ge%.
  • n-FETs with optimal Si shell thickness.
  • pFETs with thinner Si shell and high-k.
  • tdelay SiGe n-FETs 1.2 times greater than Si.
  • tdelay SiGe p-FETs 1.25 times greater than Si.


Work Published in IEEE, EDL, 31, 2010. doi: 10.1109/LED.2010.2040577

Intrinsic gate delay (tdelay) in n-FETs with core thickness and Ge%.
Intrinsic gate delay (tdelay) in p-FETs with core thickness and Ge%.

Powerpoint slide as ppt, pdf, or as image below.