Abhijeet Paul

Performance Analysis of SiGe/Si core/shell NWFETs

Performance analysis of SiGe/Si core/shell NWFETs Abhijeet Paul, Saumitra Mehrotra, Mathieu Luisier and Gerhard Klimeck

Objective:

  • Performance assessment of SiGe nanowire FETs(NWFETs), ultra-scaledregime, next-gen CMOS solution.

Approach:

  • Bandstructure: Virtual Crystal Approximation in TB (TB-VCA).
  • Transport: Ballistic Virtual Source model.
  • Performance metrics: Vinj,ION and intrinsic gate delay (tdelay).

Result:

  • n/p-FETs better for higher Ge%.
  • n-FETs with optimal Si shell thickness.
  • pFETs with thinner Si shell and high-k.
  • tdelay SiGe n-FETs 1.2 times greater than Si.
  • tdelay SiGe p-FETs 1.25 times greater than Si.

Impact:

Work Published in IEEE, EDL, 31, 2010. doi: 10.1109/LED.2010.2040577
Intrinsic gate delay (tdelay) in n-FETs with core thickness and Ge%.
Intrinsic gate delay (tdelay) in p-FETs with core thickness and Ge%.

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Abhijeet Paul's Pages

Biography Publications Orientation dependance of charge distribution in silicon nanowire transistors. Development of tools and simulators for Discover and Learning. Top-of-the-Barrier Model surface and transport oreintation on P-type Nanowire FETs Top-of-the-Barrier Model with experimental CV dataTight-binding Virtual Crystal Approximation model for SiGePerformance Analysis of SiGe/Si core/shell NWFETsAtomistic modeling of thermoelectric power factor in Si Nanowires Modified Valence Force Field (MVFF) method for Si and Ge bulk Modified Valence Force Field (MVFF) method for Si nanowires Interface trap density extraction in Si nfinFETs. Simulation of CV curves for biaxially strained SiGe pMOSFETs. Tunability of lattice thermal conductance in Siand Ge nanowires using porosity Strain effects on the phonon thermal properties of ultra-scaled Si nanowires

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