Abhijeet Paul

Abhijeet Paul is a PhD student in the group. Abhijeet joined the Klimeck research group in August 2006.

Abhijeet Paul was born in Bhopal, Madhya Pradesh, India.He received his Bachelor's Degree in Electrical Engineering and Master's degree in Microelectronics and VLSI design, both from Indian Institute of Technology, Bombay in 2006.

Abhijeet's research is focused on the computational modeling and simulation of electronic structure and transport properties in ultra-scaled semiconductor devices. He has been involved in the development of many computational tools and simulators that have been deployed on nanoHUB. Presently he is involved in the development of OMEN.

Detailed nanoHUB contribution by Abhijeet can be found on his contributor webpage on nanoHUB.org.

In the Klimeck group he has worked on the following research projects:

• Electrostatics of semiconductor nanowire mosFETs Orientation dependance of charge distribution in silicon nanowire transistors. The work was presented at Techcon 2008 held at Austin, Texas on November 3/4 , 2008 [P96]
• Electronic band-structure calculation in bulk semiconductors as well as confined structures like nanowires, ultra-thin bodies (UTB). This work led to the developement of latest version of Bandstructure Lab V2.0 tool.
• Development of tools and simulators for Discover and Learning.
• Electrical properties of semiconducting nanowires, developement of modeling tools and comparison of 2D and 3D transport models for nanowires.
• Study of the validity of the Top-of-the-Barrier Model in Nanowire FETs. The model is found to work in close agreement with 3D model for a range of device cross-sections and channel lengths. This work was presented at the 13th International Workshop on Computational Electronics (IWCE) held at Tsinghua University, in Beijing from May 27-29, 2009. [P109]
• Study of surface and transport oreintation on P-type Nanowire FETs. This work was presented at the proceedings of 7th IEEE Workshop on Microelectronics and Electron Devices (WMED 2009), Apr 03, 2009. [P108]
• Benchmarking of Top-of-the-Barrier Model with experimental CV data. This work was done in joint collaboration with IME Singapore, who provided the experimental data. This work has been published in IEEE EDL, vol 30, issue 5, 2009.

Presently he is working on these following research areas:

• Study of SiGe bandstructure. and quantum transport in Nanowire FETs. based on Si-Ge alloy system.
• Study of thermoelectric properties. in confined semi-conductor systems using ballistic and diffusive approach
• Study of phonon systems in semiconductor nanostructures to understand thermal properties.
• Nanoscale thermal transport in semiconductor nanowires.

Collaboration: We are always happy to collaborate with experimental groups to provide theoritical support and know how. Please feel free to contact and we can work together to achieve the goals.

email id: paul1[at the rate]purdue dot edu.