Abhijeet Paul

Top-of-the-Barrier Model with experimental CV data

Benchmarking Top of the Barrier Model using experimental CV data This project was a collaboration between Purdue University and IME Singapore Purdue Collaborators: Abhijeet Paul,Raseong Kim, Mathieu Luisier, Gerhard Klimeck and Mark Lundstrom IME Singapore Collaborators: Subash Rustagi, H Zhao.


  • Verify experimental CV measurement technique(CBCM*)for single silicon nanowire FETs.
  • Benchmarking Top of the Barrier(ToB)transport model using experimental CV data.
*CBCM = Charge-Based Capacitance Measurement

Device Details:

Self-Consistent Scheme
  • Device Dimensions: Tox = 9nm, W = 25nm, H = 14 nm
  • Source/Drain doping: n-type ,1e20cm-3
  • Intrinsic <100> oriented Silicon channel.


  • Use sp3d5s* Tightbinding model for electronic structure calculation for the silicon wire core.
  • Perform self-consistent Schrodinger-Poisson(2D) simulations at different gate biases (Vgs) for the actual device.



Measured C-Vgs using the CBCM technique and self-consistent intrinsic SiNW gate capacitance simulated using ToB model added with the 3-D electrostatic capacitance without considering NW obtained from COMSOL
Electric Potential Distribution at Vgs = 1V.
Electronic charge distribution at Vgs = 1V. units of charge: nm^-3.

Powerpoint slide as ppt, pdf, or as image below.