Abhijeet Paul \\ Member \\ The Nanoelectronic Modeling Group \\ Purdue University

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Top-of-the-Barrier Model with experimental CV data

Benchmarking Top of the Barrier Model using experimental CV data This project was a collaboration between Purdue University and IME Singapore

Purdue Collaborators: Abhijeet Paul,Raseong Kim, Mathieu Luisier, Gerhard Klimeck and Mark Lundstrom IME Singapore Collaborators: Subash Rustagi, H Zhao.

Objective:

Verify experimental CV measurement technique(CBCM*)for single silicon nanowire FETs.
Benchmarking Top of the Barrier(ToB)transport model using experimental CV data.

*CBCM = Charge-Based Capacitance Measurement

Device Details:

Self-Consistent Scheme

Device Dimensions: Tox = 9nm, W = 25nm, H = 14 nm
Source/Drain doping: n-type ,1e20cm-3
Intrinsic <100> oriented Silicon channel.

Approach:

Use sp3d5s* Tightbinding model for electronic structure calculation for the silicon wire core.
Perform self-consistent Schrodinger-Poisson(2D) simulations at different gate biases (Vgs) for the actual device.

Impact:

New CV measurement method.
Top of the Barrier method suitable for CV modeling of Silicon Nanowire FETs.
Work published in IEEE, EDL VOL. 30, NO. 5,MAY 2009. p.526

Results:

Measured C-Vgs using the CBCM technique and self-consistent intrinsic SiNW gate capacitance simulated using ToB model added with the 3-D electrostatic capacitance without considering NW obtained from COMSOL

Electric Potential Distribution at Vgs = 1V.

Electronic charge distribution at Vgs = 1V. units of charge: nm^-3.

Powerpoint slide as ppt, pdf, or as image below.

Abhijeet Paul's Pages

Biography Publications Orientation dependance of charge distribution in silicon nanowire transistors. Development of tools and simulators for Discover and Learning. Top-of-the-Barrier Model surface and transport oreintation on P-type Nanowire FETs Top-of-the-Barrier Model with experimental CV data Tight-binding Virtual Crystal Approximation model for SiGe Performance Analysis of SiGe/Si core/shell NWFETs Atomistic modeling of thermoelectric power factor in Si Nanowires Modified Valence Force Field (MVFF) method for Si and Ge bulk Modified Valence Force Field (MVFF) method for Si nanowires Interface trap density extraction in Si nfinFETs. Simulation of CV curves for biaxially strained SiGe pMOSFETs. Tunability of lattice thermal conductance in Siand Ge nanowires using porosity Strain effects on the phonon thermal properties of ultra-scaled Si nanowires

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