Abhijeet Paul

Interface trap density extraction in Si nfinFETs

Objective:

  • Ddirect trap density estimation in actual Si <100>/<110> n-finFETs.

Results:

  • Dit estimation in two n-finFETs .

Approach:

  • Approach: Using difference between non-ideal (expt.) and ideal (simulated)
    • Source to channel barrier height (Eb)
    • Active channel area (S).

 

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Abhijeet Paul's Pages

Biography Publications Orientation dependance of charge distribution in silicon nanowire transistors. Development of tools and simulators for Discover and Learning. Top-of-the-Barrier Model surface and transport oreintation on P-type Nanowire FETs Top-of-the-Barrier Model with experimental CV dataTight-binding Virtual Crystal Approximation model for SiGePerformance Analysis of SiGe/Si core/shell NWFETsAtomistic modeling of thermoelectric power factor in Si Nanowires Modified Valence Force Field (MVFF) method for Si and Ge bulk Modified Valence Force Field (MVFF) method for Si nanowires Interface trap density extraction in Si nfinFETs. Simulation of CV curves for biaxially strained SiGe pMOSFETs. Tunability of lattice thermal conductance in Siand Ge nanowires using porosity Strain effects on the phonon thermal properties of ultra-scaled Si nanowires

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