Abhijeet Paul

Abhijeet Paul's Publications

Journal Publications (Published and accepted):

1. Tuning lattice thermal conductance by porosity control in ultra-scaled Si and Ge nanowires, A. Paul
   and Gerhard Klimeck, APL, 2011.
2. Full 3D Quantum Transport Simulation of Atomistic Interface Roughness in Silicon Nanowire FETs,
   S.G. Kim, A. Paul, M. Luisier, T. B. Boykin, G. Klimeck, IEEE TED, 2011.
3. Interface Trap Density Metrology of state-of-the-art undoped Si n-FinFETs, A. Paul, G. Tettamanzi, S.
   Lee, S. R. Mehrotra, N. Collaert, S. Biesemans, G. Klimeck and S. Rogge, IEEE EDL, 2011.
4. Intrinsic Reliability improvement in Biaxially Strained SiGe p-MOSFETs, S. Deora, A. Paul, R. Bijesh, J.
   Huang, G. Klimeck, G. Bersuker, P. D. Krisch and R. Jammy, IEEE EDL, 2010.
5. Modified valence force field approach for phonon dispersion: from zinc-blende bulk to nanowires,
   methodology and computational details, Abhijeet Paul, Mathieu Luisier and Gerhard Klimeck, Journal of
   Computational Electronics, Vol. 9, Oct. 2010.
6. Performance Analysis of Ultra-scaled SiGe Standard and Core/Shell Nanowire MOSFETs, Abhijeet
   Paul, Saumitra Mehrotra, Mathieu Luisier and Gerhard Klimeck, IEEE EDL, Apr. 2010.
7. Thermionic Emission as a tool to study transport in undoped nFinFETs, Giuseppe C. Tettamanzi,
   Abhijeet Paul, Gabriel P. Lansbergen, Jan Verduijn, Sunhee Lee, Nadine Collaert, Serge Biesemans, Gerhard Klimeck and Sven Rogge, IEEE EDL, 2009.
8. Sub-threshold study of undoped Trigate nFinFET, G.C. Tettamanzi, G.P. Lansbergen, Abhijeet Paul, S. Lee, P.A. Deosarran, N.Collaert, G. Klimeck, S.Biesemans and S. Rogge, Thin Solid Films, Oct. 2009
9. Characterization and Modeling of Subfemtofarad Nanowire Capacitance Using the CBCM
   Technique, Hui Zhao, Raseong Kim, Abhijeet Paul, M. Luisier, G. Klimeck, Fa-Jun Ma, S.C. Rustagi, G.S.
   Samudra, N. Singh, Guo-Qiang Lo, Dim-Lee Kwong, IEEE EDL, Vol. 30. No.6, 2009.
10. Simulations of Nanowire Transistors: Atomistic vs. Effective Mass Models, Neophytos Neophytou,
    Abhijeet Paul, Mark S. Lundstrom, and Gerhard Klimeck, Journal of Computational Electronics, Vol. 7, No. 3,
    Sept. 2008.
    
11. Bandstructure Effects in Silicon Nanowire: Electron Transport, Neophytos Neophytou, Abhijeet Paul,
    Mark Lundstrom, and Gerhard Klimeck, IEEE TED, Vol. 55, Issue 6, 2008.
    
12. Dimensionality in metal-oxide-semiconductor field-effect transistors: A comparison of one-
    dimensional and two-dimensional ballistic transistors, Raseong Kim, Neophytos Neophytou, Abhijeet Paul,
    Gerhard Klimeck, and Mark S. Lundstrom, J. Vac. Sci. Technol. B, Vol. 26, 2008.
    
13. Bandstructure Effects in Silicon Nanowire: Hole Transport, Neophytos Neophytou, Abhijeet Paul and
    Gerhard Klimeck, IEEE Trans. on Nanotech., Vol. 7, 2008.

Under review:

1. Atomistic approach to alloy scattering in Si1-xGex", Saumitra Mehrotra, Abhijeet Paul and Gerhard Klimeck, Under review in APL, 2011.
   
2. Interface trap density metrology from sub-threshold transport in highly scaled undoped Si n-
   FinFETs.", Abhijeet Paul, Giuseppe Carlo Tettamanzi , Sunhee Lee , Saumitra Raj Mehrotra , Nadine Collaert ,
   Serge Biesemans , Sven Rogge , Gerhard Klimeck, under review, JAP, 2011.

Conference/Talks (Published and accepted):

1. Parameter Fitting for Lattice Properties of Gallium Arsenide using Parallel Genetic Algorithm, Mehdi Salmani-Jelodar, Sebastian Steiger, Abhijeet Paul and Gerhard Klimeck, IEEE Congress on Evolutionary
   Computation, 2011.
2. Tuning lattice thermal conductance in ultra-scaled Si Nanowires: Role of porosity size, density and
   distribution, Abhijeet Paul, K. Miao, M. Luisier and G. Klimeck, MRS Spring Meeting, San Fransisco,
   2011.
   
3. A New Method to Achieve RF Linearity in SOI Nanowire MOSFETs, A. Razavieh, N. Singh, Abhijeet
   Paul, G. Klimeck, D. B. Janes, J. Appenzeller, RFIC2011, 2011.
   
4. Strain Engineering of the thermal conductance in Si nanowires, Abhijeet Paul, K. Miao, M. Luisier
   and G. Klimeck, American Physical Society, March Meeting, 2011, Dallas, TX, USA.
   
5. Tight-binding based alloy scattering calculations in Si1-xGex, S. Mehrotra, Abhijeet Paul and G.
   Klimeck, American Physical Society, March Meeting, 2011, Dallas, TX, USA.
   
6. Atomistic modeling of the phonon dispersion in free-standing <100> Si nanowires, Abhijeet Paul,
   M. Luisier and G. Klimeck, 14th Int. Workshop on Comp. Electronics (IWCE), Oct. 2010, University of
   Pisa, Italy.
   
7. Strain Engineering of Ultra-scaled Trigated Si finFETs for Performance Enhancement, Abhijeet Paul,
   M. Luisier and G. Klimeck, Proceedings of TECHCON, Sept. 2010, Austin, TX, USA.
   
8. Innovative characterization techniques for ultra-scaled FinFETs, G. C. Tettamanzi, G. P. Lansbergen,
   J. Verduijn, R. Rahman, Abhijeet Paul, S. Lee, N. Collaert, S. Biesemans, G. Klimeck, and S. Rogge, 10th
   IEEE Conference on Nanotechnology, 2010.
   
9. Computational Modeling of the Electronic and Lattice Properties for Nanoscale Semiconductor
   Device Simulations, Abhijeet Paul and G. Klimeck, IEEE-EDS invited talk , 9th Aug. 2010, IIT-Bombay,
   India.
   
10. Atomistic Modeling of the Thermoelectric Power Factor in Ultra-scaled Silicon Nanowires, Abhijeet
    Paul, G. Klimeck, IEEE, Silicon Nanoelectronics Workshop, June, 2010, Hawaii, USA.
    
11. Fullband Study of Ultra-scaled Electron and Hole SiGe Nanowire FETs, Abhijeet Paul, S. Mehrotra,
    M. Luisier, and G. Klimeck, 8th IEEE Workshop on Microelectronics and Electron Devices (WMED),
    April 2010, Boise, Idaho, USA.
    
12. Atomistic approach to study charge and current distribution in ultra-scaled SiGe/Si core/shell
    nanowire FETs, Abhijeet Paul, S. Mehrotra, M. Luisier, G. Klimeck, American Physical Society, March
    Meeting, 2010, Portland, OR, USA.
    
13. Full 3D Quantum Transport Simulation of Interface Roughness in Nanowire FETs, S. G. Kim, Abhijeet
    Paul, M. Luisier, G. Klimeck and T. B. Boykin, American Physical Society, March Meeting, 2010,
    Portland, OR, USA.
    
14. Study of Ultra-scaled SiGe/Si Core/Shell Nanowire FETs for CMOS Applications, Abhijeet Paul,
    Saumitra Mehrotra, Mathieu Luisier and Gerhard Klimeck, International Semiconductor Device
    Research Symposium (ISDRS), Dec. 2009, MD, USA.
    
15. On the validity of Top-of-the-barrier Model in ultra-scaled n-type Silicon nanowire FETs, Abhijeet
    Paul, Saumitra Mehrotra, Mathieu Luisier and Gerhard Klimeck, Proceedings of TECHCON, Sept. 2009,
    
16. Austin, TX, USA.Introduction to Bandstructure Lab: A web-based tool for research work, Abhijeet
    Paul and Gerhard Klimeck, NCN summer school, May 2009, Purdue University, USA.
    
17. Surface and Orientation dependence on performance of Trigated Silicon Nanowire pMOSFETs', Abhijeet Paul, Saumitra Mehrotra, Mathieu Luisier, and Gerhard Klimeck, 7th IEEE Workshop on
    Microelectronics and Electron Devices (WMED), April 2009, Boise, Idaho, USA.
    
18. On the validity of the top of the barrier quantum transport model for ballistic nanowire MOSFETs', Abhijeet Paul, Saumitra Mehrotra, Mathieu Luisier, and Gerhard Klimeck, 13th International Workshop on Computational Electronics (IWCE), May 2009, Tsinghua University, Beijing, China.
    
19. Study of Electronic Charge Distribution in Silicon Nanowire Transistors: An Atomistic Approach, Abhijeet Paul, Saumitra Mehrotra, Mathieu Luisier and Gerhard Klimeck, APS March Meeting, March
    2009, Pittsburgh, PA, USA.
    
20. Orientation dependence of the charge distribution and quantum capacitance in silicon nanowire
    transistors, Abhijeet Paul, Neophytos Neophytou and Gerhard Klimeck, Proceedings of TECHCON,
    SRC, Sept. 2008, Austin, TX, USA.
    
21. Nanowire Simulations from atomistic tool development to deployed tools on nanoHUB.org, Gerhard
    Klimeck, Mathieu Luisier, Saumitra Mehrotra, Xufeng Wang,SungGeun Kim, Neophytos Neophytou,
    Abhijeet Paul, Ben Haley, 3rd nanowire growth workshop,Sept.2008, Duisburg, Germany.
    
22. Self-consistent simulations of nanowire transistors using atomistic basis sets, Neophytos
    Neophytou, Abhijeet Paul, Mark S. Lundstrom and Gerhard Klimeck, Proceedings of The 12th
    International Conference on Simulation of Semiconductor Devices and Processes (SISPAD), Sept.2007,
    Vienna Austria.
    
23. Comprehensive Study of Program, Erase and Retention in Charge Trapping Flash Memories,
    Abhijeet Paul, S. Sridhar, Suny Gedam and Souvik Mahapatra, \textit{International Electron Device
    Meeting, IEDM}, Dec. 2006, SanFransisco, CA, USA.

Conferences (Submitted) :

1. Techcon 2011, SungGuen Kim.
2. Techcon 2011, Saumitra Mehrotra
3. Enhancement of thermoelectric efficiency by uniaxial tensile stress in n-type GaAs nanowires", Abhijeet Paul, K Miao, G Hedge, Saumitra Mehrotra, Mathieu Luisier and Gerhard Klimeck, Submitted to IEEE
   NANO, 2011.