VIP, SoCET Student Design Accepted for Fabrication by Google/eFabless
SoCET (System on Chip Extension Technologies, https://engineering.purdue.edu/SoC-Team) was formed to provide students hands on experience with a fully developed industry quality SoC design flow. Members of the group engage with RTL design, physical design, PCB design, chip bring-up, verification methods, an array of EDA tools and software development. SoCET sub-teams are involved in numerous projects including analog circuit design, processor architecture, hardware security, hardware verification, IC test, compiler development, and embedded software development.
SoCET's most recent accomplishment is the acceptance by Google/eFabless in June 2021 for fabrication of our latest design, AFTx06, at the Skywater 130nm foundry:
Following is a block diagram of the design along with a physical layout of the IC and a picture of Dakota Funke, a VIP Senior Design student who worked with graduate student team members to prepare the final layout for fabrication including design contributions from many students over many years.
Dakota has this to say about his experience on SoCET and on preparing this design for tape-out.
"Looking back at joining the Purdue System-on-Chip Extension Technologies team and beginning my work with the Design Flow sub team less than a year ago, this opportunity has been a highlight of my Purdue experience. To be able to enrich my knowledge and expand my horizons in such valuable ways, has all been enabled through the mentoring by Dr. Johnson and my team leads John Martinuk and Raghuraman Kannan Kottaiyur.
After learning the basics of Design Flow and the steps needed to convert an RTL (Register Transfer Level) design into a physical layout, the focus of my work shifted towards being able to implement a fully open-sourced RTL to GDSII flow. GDSII is an industry standard format for IC designs.
Utilizing the SkyWater 130nm experimental open-source Process Design Kit (PDK), our team’s goal was to generate a clean layout ready for tape-out using this new open-source toolchain. In the process of getting our design ready for tape-out, I specifically had the opportunity to become thoroughly acquainted with many of the tools that we would be using quite often, the most notable of which were OpenLANE and Magic. In our initial efforts at getting our design ready for tape-out, I found myself often utilizing OpenLANE and the flow to generate layouts of smaller designs, so as to get us closer towards being able to understand and run the flow in appropriate manner for our design. Upon finalizing the steps necessary for the flow in generating our final layout, being unable to pass the design for the AFTx06 through the flow due to hardware constraints, my focus shifted to performing manual verification in Magic of our final generated layout and documenting much of the work and features of our design for our project proposal.
Having recently submitted our project and it being accepted to the Efabless MPW-TWO shuttle run, it brings me great joy to see the team’s design being fabricated in this exciting experimental opportunity. Especially knowing all of the effort that was put in by the team thus far. Over the rest of the summer, I look forward to continuing my work in exploring and implementing other PDK’s and am grateful for all that I have learned and been able to experience through the program thus far. "
About VIP:
The Vertically Integrated Projects (VIP) Program provides an opportunity for undergraduate students to earn academic credit while engaging in authentic and extended research and design projects related to active research areas of Purdue faculty members and national, international, and industry-sponsored design challenges. Students can participate on interdisciplinary and vertically-integrated teams (first-year through seniors) with faculty and graduate student mentors for multiple semesters to address these real-world research and design challenges.