Purdue SoCET

The goal of Purdue SoCet (system-on-chip extension technologies) is to provide students hands on experience with a fully developed industry quality SoC design flow. Members of the group engage with RTL design, physical design, PCB design, chip bringup, verification methods, an array of EDA tools and software development.

Recent tape-outs

On August 10, 2022, an experimental design on TSMC 180nm was taped out via MUSE Semiconductor. This IC is a test chip to demonstrate applications of polymorphic logic in logic locking, recongurability, and countermeasures against reverse engineering.

AFTx06 on June 20, 2021 for fabrication on the Skywater 130nm process in connection with the Google sponsored open-source MPW runs as described here.

AFTx07 is currently being processed by SkyWater (May 2024) for fabrication on the Skywater 130nm process

Recent packaged SoC

Packaged ICs and two test PCBs were received from January 2022 from eFabless corporation the AFTx06 design mentioned above. Testing continues.

Details of some of our subteams can be found here.

Items on Roadmap for AFTx07 and Later

• 6 stage RISCV pipeline created
• Vector extension to RISCV CPU
• ISA extensions: atomic, compressed, floating point, privileged
• Developing an LLVM based compiler to exploit the sparsity optimizations in our current RISCV core.
• Adding support for RUST programming language
• freeRTOS
• FPGA prototyping of our design with an eye to using it as a software development platform for our design.
• Multi-core
• L1/L2 cache
• Multi-core interrupts
• Branch predictor
• RISCV verification
• RISCV debug
• DMA controller
• Power management

Other projects and collaborations

• Several analog mixed signal student projects including a low drop-out regulator, op-amp, DAC, and adding wireless support to a future version of our chip, as part of a collaboration with the HINET lab.
• Collaboration with C-BRIC on in-memory computing, Hard AI - K Roy, A Raghunathan
• GPU accelerator design - T Rogers
• Side-channel attach countermeasures - S Sen
• Reverse engineering countermeasures - J Appenzeller
• MRAM hardware security - J Appenzeller

Details on older versions of the AFTx chip can be found here.

Team Brochure

Digital Design

• RISCV CPU extensions: Vector, Compressed, Atomic, instructions, Floating point, Privileged instructions
• Multi-core, L1/L2 Cache, multi-core interrupts, Branch predictor, RISCV Verification (RISCV-DV), RISCV Debug, Off chip SRAM, Improved Timer, Bus updates, DMA controller, compact self-test ROM, Power management

Verification

• UVM, Modelling UVM on FPGA, Formal

Analog/Mixed Signal

• LDO, Op-amp, DAC, Wireless

Software

• Compiler tool chain development, IO libraries, RTOS port, demo applications

Backend Design Flow

• Open source synthesis/layout/verification
• Commercial EDA tool synthesis/layout/verification
• Physical verification - power, timing
• Tape-out to foundry

PCB/test

• PDB designs for test/demonstrations of recent ICs

Special Projects

• Collaborations with research groups
• MRAM hardware security (Appenzeller group)
• Reverse engineering counter measures, applications of polymorphic logic (Appenzeller Group)
• GPU accelerator design (T. Rogers group)
• Rowhammer attack detection/mitigation in in connection with Professional Master's projects.

Test Engineering

• DFT, APTG incorporate into Spring 2024 tape-out

 

If you are interested in being a part of the SoCET team either through credit or on a volunteer basis in the Spring 2025 semester please apply using this form. See Team Brochure for descriptions of subteam and project opportunities.

If you're accepted, please use this Qualtrics form to register SoCET in the VIP program.