Purdue SoCET
About
The goal of Purdue SoCet (system-on-chip extension technologies) is to provide students hands on experience with a fully developed industry quality SoC design flow. Members of the group engage with RTL design, physical design, PCB design, chip bringup, verification methods, an array of EDA tools and software development.
Recent tape-outs
On August 10, 2022, an experimental design on TSMC 180nm was taped out via MUSE Semiconductor. This IC is a test chip to demonstrate applications of polymorphic logic in logic locking, recongurability, and countermeasures against reverse engineering.
AFTx06 on June 20, 2021 for fabrication on the Skywater 130nm process in connection with the Google sponsored open-source MPW runs as described here.
AFTx07 is currently being processed by SkyWater (May 2024) for fabrication on the Skywater 130nm process
Recent packaged SoC
Packaged ICs and two test PCBs were received from January 2022 from eFabless corporation the AFTx06 design mentioned above. Testing continues.
Details of some of our subteams can be found here.
System-on-Chips
Items on Roadmap for AFTx07 and Later
- 6 stage RISCV pipeline created
- Vector extension to RISCV CPU
- ISA extensions: atomic, compressed, floating point, privileged
- Developing an LLVM based compiler to exploit the sparsity optimizations in our current RISCV core.
- Adding support for RUST programming language
- freeRTOS
- FPGA prototyping of our design with an eye to using it as a software development platform for our design.
- Multi-core
- L1/L2 cache
- Multi-core interrupts
- Branch predictor
- RISCV verification
- RISCV debug
- DMA controller
- Power management
Other projects and collaborations
- Several analog mixed signal student projects including a low drop-out regulator, op-amp, DAC, and adding wireless support to a future version of our chip, as part of a collaboration with the HINET lab.
- Collaboration with C-BRIC on in-memory computing, Hard AI - K Roy, A Raghunathan
- GPU accelerator design - T Rogers
- Side-channel attach countermeasures - S Sen
- Reverse engineering countermeasures - J Appenzeller
- MRAM hardware security - J Appenzeller
Details on older versions of the AFTx chip can be found here.
Digital Design
- Focuses on the architecture and implementation of RISC-V–based systems and advanced SoC components
- Projects span improvements to the RISC-V CPU core, work on the chip interconnect, and development of digital peripherals.
- Example RISC-V projects: Multi-core processor, multi-core interrupts, RISC-V extensions, branch predictors, DMA, power management
- Example peripheral projects: SPI, PWM, Timer
Verification
- Ensures correctness and reliability of SoC designs
- Focuses on industry standard UVM-based verification and reusable testbenches
- Validates processors, memory systems, and custom hardware blocks
Analog/Mixed Signal
- Focuses on designing non-digital components that bridge real-world signals and on-chip processing
- Enables integration between physical sensors, power systems, communication interfaces, and digital logic
- Example projects: LDO, Op-amp, DAC, Wireless
Software
- Compiler toolchains, IO libraries, RTOS porting, demo applications
Physical Design
- Open-source and commercial synthesis/layout/verification
- Physical verification: power and timing
- Tape-out preparation
PCB/Test
- PCB designs for testing and IC demonstrations
Test Engineering
- DFT, ATPG, and post-silicon validation
Special Projects
- Collaborations with research groups
- MRAM hardware security, polymorphic logic
- GPU accelerator design
- Rowhammer attack detection/mitigation
Papers
M.C. Johnson. ASSURE Final Report. Aug 2020.
J. Covey, M. C. Johnson – System-on-a-Chip Design as a Platform for Teaching Design and Design Flow Integration, Proceedings of the 2019 on Great Lakes Symposium on VLSI, Tysons Corner, VA, 2019.
J. R, Stevens, J. Skubic, E. Colter, and Dr. M. Swabey. Purdue microbrewer: A microcontroller generator. RISCV Microelectronics Conference 2017, Mar 2017.
J. Skubic, J. R. Stevens, C. Y. Tan, Dr. M. Johnson, and Dr. M. Swabey. Riscv-business: A configurable, extensible risc-v core. RISCV Microelectronics Conference 2017, Mar 2017.
M. A. Swabey and M. C. Johnson. Satisfying ABET criterion using an industrial microelectronic skills incubator. 2015 IEEE International Conference on Microelectronics Systems Education, May 2015.
Contact Info
If you need more information about SoCET and how to join the team, please email socet@purdue.edu.
ATTENTION: The pre-registration deadline for SoCET is 11:59pm, Friday October 24. Acceptance decisions for pre-registration students will be announced by November 10.
If you are a freshman or sophomore and have minimal background in electronics, please apply for STARS/Intro to SoCET using Spring STARS application survey.
If you already have completed courses such as ECE 20007 and ECE 27000 or you have other significant electronics experience, please apply to be part of the main SoCET team in Spring 2026 using Spring 2026 SoCET application survey.
See Team Brochure for descriptions of subteam and project opportunities.
If you're accepted and if you have not already registered for a VIP SoCET section, please email socet@purdue.edu for details on course sections to register for.
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