Welcome to the Purdue SoCet (System-on-Chip Extension Technologies) homepage! Our goal is to provide students hands on experience with a fully developed industry quality SoC design flow. Members of the group engage with RTL design, physical design, PCB design, chip bringup, verification methods, an array of EDA tools and software development.
On August 10, 2022, an experimental design on TSMC 180nm was taped out via MUSE Semiconductor. This IC is a test chip to demonstrate applications of polymorphic logic in logic locking, recongurability, and countermeasures against reverse engineering.
AFTx06 on June 20, 2021 for fabrication on the Skywater 130nm process in connection with the Google sponsored open-source MPW runs as described at https://www.skywatertechnology.com/press-releases/google-partners-with-skywater-and-efabless-to-enable-open-source-manufacturing-of-custom-asics/.
Recent packaged SoC: Packaged ICs and two test PCBs were received from January 2022 from eFabless corporation the AFTx06 design mentioned above. Testing continues.