Saumitra Mehrotra

Engineering nanowire n-MOSFETs at Lg < 8nm

Engineering nanowire n-MOSFETs at Lg < 8nm S. Mehrotra, S.G. Kim, M. Povolotskyi, T. Kubis, M. Lundstrom & G. Klimeck

Objective:

  • MOSFET scaling solutions at Lg<8 nm

Approach:

  • Engineer heavy transport masses in nanowire devices using orientation and strain engineering.
  • Full band (sp3d5d* TB model) quantum transport simulations using OMEN.

Results:

  • Heavy mass limits S-D tunneling and improves over ON-OFF current ratio.
  • Near ideal Id-Vd even at hannel
    lengths, Lg=3 nm.
  • Scaling solutions at Lg < 8 nm lie within Si material.

Impact:

  • Trans. Elec. Dev. (submitted.)



 

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Saumitra Mehrotra's Pages

Biography Development of Nanowire code on nanoHUB Development of simulation tools for semiconductor course work Performance of Trigated Silicon Nanowire pMOSFETs: Surface and Orientation dependence On validity of the Top of the Barrier model for Quantum Transport in Nanowire MOSFETs Effect of biaxial+uniaxial compressive strain on SiGe /Si hole bandstructure and pMOSFET Atomistic approach to alloy scattering in SiGe Performance enhancement of GaAs UTB pFETs by strain, orientation and body thickness engineering Benchmarking of bulk SiGe and strained SiGe/(100)Si bandstructure using Tight-binding VCA model Ballistic hole injection velocity analysis in Ge UTB pMOSFETs Engineering nanowire n-MOSFETs at Lg < 8nm Atomistic simulation of phonon and alloy limited hole mobility in Si1-xGex nanowires Simulation Study of Thin-Body Ballistic n-MOSFET Involving Transport in Mixed Γ-L valleys Effect of Fin Tapering in Nanoscale Si FinFETs Group Publications

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