Saumitra Mehrotra

Development of Nanowire code on nanoHUB.

Mode space approach for silicon nanowire simulations Saumitra Raj Mehrotra , Ben Haley & Gerhard Klimeck

Objective:

  • Development of silicon nanowire simulator with EMA mode space approach.
  • Elicit difference between coupled and uncoupled mode space approaches.

Approach:

  • Improved frontend GUI for nanowire code using rappture
  • Full 3D naonwire code based on Fortran90 with MPI used for parallelization
  • Uncoupled (UMS) and Fast Uncoupled mode space (FUMS) approaches for fast simulation.

Impact:

  • Deeper understanding of mode coupling and when it is important
  • Serving scientific community with more than 1200 users and 18000 simulation runs.

Results:

  • Nanowire V2.0 installed on nanohub including improved features.
  • Material Properties.
  • Crystal Orientation.
  • 3D Eigenfunctions.
  • 1D Electron density.
  • 1D conduction subband profile.

Publication:

  • Mehrotra, S.R.; Roenker, K.P. (2007), " Process Variation Study for Silicon Nanowire Transistors," Microelectronics and Electron Devices, 2007 IEEE Workshop on: pg. 40--41, 04.

Powerpoint slide as ppt, pdf, or as image below.

Saumitra Mehrotra's Pages

Biography Development of Nanowire code on nanoHUB Development of simulation tools for semiconductor course work Performance of Trigated Silicon Nanowire pMOSFETs: Surface and Orientation dependence On validity of the Top of the Barrier model for Quantum Transport in Nanowire MOSFETs Effect of biaxial+uniaxial compressive strain on SiGe /Si hole bandstructure and pMOSFET Atomistic approach to alloy scattering in SiGe Performance enhancement of GaAs UTB pFETs by strain, orientation and body thickness engineering Benchmarking of bulk SiGe and strained SiGe/(100)Si bandstructure using Tight-binding VCA model Ballistic hole injection velocity analysis in Ge UTB pMOSFETs Engineering nanowire n-MOSFETs at Lg < 8nm Atomistic simulation of phonon and alloy limited hole mobility in Si1-xGex nanowires Simulation Study of Thin-Body Ballistic n-MOSFET Involving Transport in Mixed Γ-L valleys Effect of Fin Tapering in Nanoscale Si FinFETs Group Publications

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