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Nanoelectronics Research Laboratory

Awards & Honors

General (Dr. Kaushik Roy)

  1. Edward G. Tiedemann Jr. Distingusihed Professor of ECE
  2. Fellow, IEEE.
  3. Humboldt Research Award, 2010
  4. IEEE Circuits and Systems Society Technical Achievement Award, 2011
  5. Distinguished Alunus Award, Indian Institute of Technology, Kharagpur, 2011
  6. Fulbright-Nehru Distinguished Chair
  7. Purdue University Faculty Scholar
  8. Semiconductor Research Corporation Technical Excellence Award, 2005
  9. Purdue University College of Engineering Research Award, 2008
  10. Research Visionary Board Member, Motorola Labs, 2002.
  11. IBM Faculty Partnership Award, 2001
  12. ATT/Lucent Foundation award, 1997.
  13. NSF CAREER development award, 1995.

Best paper awards:

  1. 2013 IEEE Transactions on VLSI Systems Vest paper Award for paper titled, "Design Paradigm for Robust Spin-Torque Transfer Magnetic RAM (STT MRAM) From Circuit/Architecture Perspective "
  2. 2012 IEEE Symposium on Low-Power Electronics and Design best paper award for paper titled, "TapeCache: High Density, Energy Effcient Cache Based on Domain Wall Memory"
  3. 2006 IEEE Transactions on VLSI Systems Best Paper Award for paper titled, "A Process-Tolerant Cache Architecture for Improved Yield in Nanoscale Technologies."
  4. 2006 ACM/IEEE International Symposium on Low Power Electronics and Design (ISLPED) Best Paper Award for paper titled, "Analysis of Super Cut-off Transistors for Ultralow Power Digital Logic Circuits."
  5. Low Power Design Contest Award (with C. Kim and J. Kim) for "A Low-Power Embedded SRAM Cache with PVT-Aware Leakage Reduction and Improved Stability in ISLPED 2005."
  6. 2005 IEEE Circuits and Systems Society Outstanding Young Author Award (Chris Kim) for paper titled, "Ultra-Low Power DLMS Adaptive Filter for Hearing Aid Applications" in IEEE Trans. on VLSI Systems.
  7. "A Novel Low-Power Scan Design Technique Using Supply Gating," IEEE International Conference on Computer Design, 2004.
  8. "Defect Oriented Testing of Analog Circuits Using Wavelet Analysis of Dynamic Current", Best paper award, 4th IEEE Latin American Test Workshop, 2003.
  9. "Circuit-Compatible Modeling of Carbon Nanotube FETs in the Ballistic Limit of Performance," Best Student Paper Award,  IEEE NANO, 2003.
  10. "On Effective IDDQ Testing of Low-Voltage CMOS Circuits Using Leakage Control Techniques," Best paper award, IEEE International Sympoisum on Quality of IC Design, 2000.
  11. "Intrinsic leakage in low-power deep sub micron CMOS ICs" , Honorable Mention Paper Award, International Test Conference, 1997.

Best paper nominations:

  1. IEEE International Conference on Computer-Aided Design 2007, "Estimation of Statistical Variation in Temporal NBTI Degradation and its Impact in Lifetime Circuit Performance.
  2. Design Automation Conference, 2007, "Characterization and Estimation of Circuit Reliability Degradation under NBTI using On-Line IDDQ Measurement"

Student awards:

  1. Arijit Raychowdhruy received Dimitris N. Chorafas Foundation Award for Outstanding PhD Thesis for the year 2007
  2. Nilanjan Banerjee received 2007-2008 Intel Fellwoship award
  3. Nilanjan Banerjee received 2007 Ford Foundation scholarship