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Nanoelectronics Research Laboratory

Patents

Designing circuits beyond traditional Silicon

Patents

  1. A. Raychowdhury, A. Keshavarzi, J. Kurtin, V. De, K. Roy, Optimal structure for high performance carbon nanotube transistors, US patent pending (filed through Intel Corporation).
  2. A. Raychowdhury, J. Kim, D. Peroulis, K. Roy, Integrated MEMS Switches for Leakage Control of Battery Operated Systems, US Patent Pending
  3. A. Raychowdhury, K. Roy, Design of novel three-valued memory using Schottky barrier carbon nanotube transistors, US Patent pending.
  4. M. Budnik, A. Raychowdhury, A. Bansal and K. Roy, High Density Capacitors for Integrated Circuit Technologies, US Patent Filed.

Memory Technology and Design

Patents

  1. H. Ananthan, A. Bansal and K. Roy, "FinFET SRAM - device and circuit design considerations." Filed with Purdue Office of Technology Commercialization in Aug. 2004, Patent Pending. Sponsored by SRC. SRC Patent ID: P0498.
  2. C. H. Kim, J. Kim, K. Roy, "A Variation-Tolerant SRAM Leakage Reduction Technique with Improved Read Stability ", pending
  3. Q. Chen, H. Mahmoodi, S. Bhunia, and K. Roy, Apparatus and Methods for Determining Memory Device Faults, Filed with Purdue Office of Technology Commercialization in May 2005, Patent pending
  4. S. Mukhopadhyay, H. Mahmoodi, and K. Roy Sense Amplifier Circuit, , Filed with Purdue Office of Technology Commercialization in Jul. 2005, Patent pending
  5. S. Mukhopadhyay, H. Mahmoodi, K. Kim, and K. Roy Self Repairing Technique in Nano-Scale SRAM to Reduce Parametric Failures, , Filed with Purdue Office of Technology Commercialization in Oct. 2005, Patent pending
  6. J. P. Kulkarni and K. Roy "A High Performance Multiplexed Keeper" patent filed with Purdue Research Foundation, March 2006
  7. J. P. Kulkarni and K. Roy "SRAM cell with built-in process tolerance" patent filed with Purdue Research Foundation, March 2007

VLSI Test and Fault Tolerance

Patents

  1. A. Keshavarzi, K. Roy, and V. De, Multi Parameter Testing with Improved Sensitivity, US patent 672695, October, 2002.
  2. A. Keshavarzi, K. Roy, and V. De, A Testing Solution for Scaled High Performance CMOS IC Multiple Parameter IDDQ Testing with Improved Sensitivity by Temperature, US patent pending.
  3. S. Bhunia, H. Mahmoodi, A. Raychowhury, S. Mukhopadhyay, and K. Roy, Low Power Scan Design and Delay Fault Testing Technique Using First Level Supply Gating, Filed by Purdue Technology Commercialization, Aug. 2004, Patent pending
  4. Q. Chen, H. Mahmoodi, S. Bhunia, and K. Roy, Apparatus and Methods for Determing Memory Device Faults, Utility Patent filed with MARCO SRC, 64354.00.US, June 2006, pending.

Ultralow Voltage Subthreshold Circuits and systems

Patents

  1. J. Kim and K. Roy, "Double Gate MOSFET Subthreshold Circuit for Ultralow Power Applications", US Patent Pending
  2. J. P. Kulkarni and K. Roy SRAM cell with built-in process tolerance patent filed with Purdue Research Foundation, March 2007