SoCET - System on Chip Extension Technologies

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SoCET: The SoCET team provides students with a comprehensive System on Chip design, fabrication and testing that is as similar to industry practice.

Advisors:

For inquiries, please email socet@purdue.edu. 

To join SoCET, you will need to complete the application which will open for PreRegistration on Tuesday, February 11 and close on Friday, March 7.

Summer 2024: https://purdue.ca1.qualtrics.com/jfe/form/SV_5zrDBdsUCiiRZs2

Fall 2024:https://purdue.ca1.qualtrics.com/jfe/form/SV_51rDILquiIMZCfA

Description:

This team is eligible for senior design.

The primary objective of the SoCET team is to provide students with a comprehensive System on Chip design, fabrication and test experience that is as similar to industry practice as possible.

Technologies:

  • RISCV open source processor
  • Verilog hardware description languages
  • FPGA
  • UVM (Universal Verification Methodology)
  • Verilog/System Verilog coding
  • Digital circuit simulation (Modelsim™, Questasim™, NCsim™, others)
  • Analog circuit simulation (Spectre™)
  • PCB layout
  • Transistor level design (Virtuoso™)
  • Chip layout (Innovus™ and Virtuoso™
  • Git repository management

Prerequisites:

Depends on which aspect of project is of interest
  • Software design: ECE264 and ECE 362
  • Logic design: ECE270, ECE 337 (ECE437 helpful but most haven’t taken yet)
  • Transistor and analog design, layout: ECE255, (ECE455/456/559 helpful)
  • PCB layout: no prerequisite available. Must be willing to learn.
  • Similar experience is acceptable, contact Dr. Johnson (mcjohnso@purdue.edu)

Partners:

•    NSWC Crane
•    Indiana Innovation Institute