SoCET - System on Chip Extension Technologies
The System on Chip (SoCET) team provides students with a comprehensive system on chip design, fabrication and testing that is as similar to industry practice.
Advisors:
Description:
The primary objective of the SoCET team is to provide students with a comprehensive System on Chip design, fabrication and test experience that is as similar to industry practice as possible.
Team Structure
SoCET is organized into two distinct levels in Indianapolis, allowing for students to enter at different points based on their academic experience.
STARS: Introduction to SoCET 1 and 2
SoCET Main Team
Each section has its own expectations, technical focus, and application process. Students in their first and second year will benefit greatly from the introduction section, where Intro 1 will follow a lecture style course in a semester and Intro 2 will capitalize on lecture material to tapeout a student team design in a semester.
Website: https://engineering.purdue.edu/SoC-Team
Technologies:
- RISCV open source processor
- Verilog hardware description languages
- FPGA
- UVM (Universal Verification Methodology)
- Verilog/System Verilog coding
- Digital circuit simulation (Modelsim™, Questasim™, NCsim™, others)
- Analog circuit simulation (Spectre™)
- PCB layout
- Transistor level design (Virtuoso™)
- Chip layout (Innovus™ and Virtuoso™
- Git repository management
Prerequisites: none
Partners: