This team is eligible for senior design.
The primary objective of the SoCET team is to provide students with a comprehensive System on Chip design, fabrication and test experience that is as similar to industry practice as possible.
- RISCV open source processor
- Verilog hardware description languages
- UVM (Universal Verification Methodology)
- Verilog/System Verilog coding
- Digital circuit simulation (Modelsim™, Questasim™, NCsim™, others)
- Analog circuit simulation (Spectre™)
- PCB layout
- Transistor level design (Virtuoso™)
- Chip layout (Innovus™ and Virtuoso™
- Git repository management
Prerequisites:Depends on which aspect of project is of interest
- Software design: ECE264 and ECE 362
- Logic design: ECE270, ECE 337 (ECE437 helpful but most haven’t taken yet)
- Transistor and analog design, layout: ECE255, (ECE455/456/559 helpful)
- PCB layout: no prerequisite available. Must be willing to learn.
- Similar experience is acceptable, contact Dr. Johnson (firstname.lastname@example.org)
Spring 2022: Thursdays 6:00-6:50 pm, EE 170
Summer 2022: TBA
Fall 2022: Thursdays 6-6:50 pm, EE 170