Fast Transient and Steady State Thermal Imaging of CMOS Integrated Circuit Chips Considering Package Thermal Boundaries
Fast Transient and Steady State Thermal Imaging of CMOS Integrated Circuit Chips Considering Package Thermal Boundaries
Event Date: | May 30, 2012 |
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Authors: | K. Yazawa, D. Kendig, J. Christofferson, A.M. Marconnet, and A. Shakouri |
Journal: | ITHERM 2012 |
Paper URL: | http://ieeexplore.ieee.org/xpl/articleDetails.jsp?arnumber=6231584 |
This study shows the results of a transient and steady-state thermal imaging, using an infrared (IR) imaging system and thermoreflectance (TR) imaging for comparison. The experiments, carried out on a wire-bond package and a flip-chip package of a CMOS thermal test chip, show the characteristics of localized heating and the mass heat capacitance depending on the package. Both chips share an array using the same unit cells, each containing heaters and diode sensors. To identify a local heating spot on a chip, spatial resolution of the thermal image is a main limiting factor. The resolution is theoretically limited by the diffraction limit, which is 3-5 microns for infrared thermal emission. While, visible light achieves 200-300nm spatial resolution with thermoreflectance. For the transient response, IR cameras provide crude spatial resolution given by the video frame rate. Thermoreflectance imaging can provide a full field mega pixel transient thermal image with wide dynamic range from 100ns up to 10's of milliseconds. The experiments are carried out on an identical sample for comparison. The full field image of a uniformly heated 5.1mm × 5.1mm wire-bond chip provides the accurate temperature values using both IR and TR methods. The accuracy is proven by multiple embedded thermal diode sensors.. In addition, transient imaging of the same chip is presented. The through-silicon-substrate transient thermal imaging, using near-infrared light for thermoreflectance, demonstrates a promising new technique to identify the small temporal (lasting a few milliseconds) hotspots in a chip with flip-chip packaging or stacked packaging under high frequency operation.