An Integrated Analysis of Thermal Conductivity Measurement in Silicon Thin Films

Event Date: July 6, 2015
Authors: Yuqiang Zeng and Amy Marconnet
Journal: International Technical Conference and Exhibition on Packaging and Integration of Electronic and Photonic Microsystems (InterPACK) 2015
Paper URL: Conference Website
International Technical Conference and Exhibition on Packaging and Integration of Electronic and Photonic Microsystems (InterPACK), San Francisco, CA, 2015.

In semiconductor industry, the reduction of the in-plane thermal conductivity in silicon thin films (TFs) makes thermal management in electronics devices challenging. Accurate knowledge of thermal transport in silicon TFs is essential for understanding and mitigating thermal issues. However, previous measurements of the in-plane thermal conductivity in silicon TFs show large variations in the data obtained from each group. These variations result in part from the different measurement techniques and variations between the samples. A comprehensive analysis of the measurement method is of great practical and theoretical interest.     

In previous measurement structures, amorphous oxide layers and/or metal layers are coated on silicon films for electric insulation or heat generation, respectively. A parallel thermal conduction analysis in the silicon and coated layer becomes invalid as the film thickness decreases to nanoscale. In this work, we measure the thermal conductivity of silicon TFs with thickness 20, 100, and 1000 nm using a suspended measurement structure with coated oxide and/or metal layers. Then, the measurement device is adapted to remove the coated layers from the test section. Comparing these results, we can check the validity of the parallel thermal conduction analysis and understand the impact of interface resistance on thermal measurement. For this comparison study, we fabricate these devices starting with the same silicon-on-insulator (SOI) wafer, in order to ensure that the silicon thin films have identical properties.

In addition to potential measurement errors and uncertainty, samples fabrication differences (e.g. method of thinning the wafers, etc.) can contribute to the data variation. Data in the literature have been fabricated starting with SOI wafers with dissimilar intrinsic properties (crystallinity, uniformity, and dopant and defects concentration). The succeeding fabrication processes can lead to suspended devices with dissimilar interface and strain situation. A variance-reduced Monte Carlo (VRMC) method is applied to study phonon transport in silicon films including impacts of these factors.  

In summary, we measure the thermal conductivity of silicon TFs using suspended measurement structures with and without coating layers. This comparison study sheds light on the variations in existing data potentially caused by different measurement techniques and samples.