Research

The RISE Lab connects materials growth, heterogeneous device integration, and nanoscale thermal transport to develop semiconductor systems for advanced computing and explore materials for quantum technologies. Our research spans the thin films that enable integration, the devices that use them, and the measurements needed to understand their electrical and thermal behavior.

Heterogeneous Device Integration  ·  Functional Material Growth  ·  Nanoscale Thermal Transport  ·  Other Research Projects

01. Heterogeneous Device Integration

New computing hardware requires devices that combine useful memory dynamics with established semiconductor processes. We engineer ferroelectric transistors and resistive memories for energy-efficient computing and heterogeneous integration. Our published silicon and hafnium-zirconium-oxide transistor combines short-term and long-term memory, demonstrating reservoir computing with 16 reservoir states and a 20 µs response time. Earlier work showed that an integrated thermal barrier enables more gradual resistive switching with an on/off ratio above 1000. Our next direction is to extend these functions to oxide-semiconductor devices and integrated computing systems.

Selected publications

Students: Yifan Wang, Heng-Ray Chuang, Hyeonjun Bae.

CONCEPTUAL SCHEMATIC

From device physics
to computing systems.

Short-term memory
Transient dynamics
Long-term memory
Programmable state

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CMOS+X integration with sensor and memory layers, thermal management, CMOS logic, packaging, and power delivery

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Integrated computing and system testing

Conceptual illustration of memory-device and CMOS integration. Published device structure and characterization and reservoir computing figures are available in Wang et al., Advanced Electronic Materials (2026).

02. Functional Material Growth

Thin-film composition, interfaces, and microstructure determine how new materials can be integrated into semiconductor systems. We use atomic layer deposition and sputtering to develop electronic and thermal materials. Published work includes ALD-grown ferroelectric memory devices and defect engineering in nickel oxide. Recent MoCx work has produced amorphous films below 5 nm with resistivity as low as 230 µΩ·cm at a growth temperature of 300 °C without post-deposition annealing, and demonstrated copper-diffusion-barrier behavior. Future directions include carbide and carbonitride contacts, nitride films for thermal management, and superconducting thin films for quantum technologies.

Selected publications

Students: Zeyu Cao, Noah Vaillancourt, Saumik Dey Shovan, Heng-Ray Chuang.

CONCEPTUAL SCHEMATIC

Build the film.
Engineer the interface.

● ● ● ●
 
 

Surface-controlled reactions

↓

Reactant APurgeReactant BPurge

↓ Repeat to build a film

Functional layer
 
Interface layer
Substrate

Composition · Interfaces · Microstructure

Illustrative schematic of surface-controlled deposition and interface engineering.

03. Nanoscale Thermal Transport

Heat flow in thin films and integrated devices is controlled by interfaces, grain boundaries, and local structure. We develop scanning thermal microscopy to measure these variations at the nanoscale. Our published probe-calibration method separates parasitic heat pathways and enables quantitative thermal mapping with sub-100 nm spatial resolution. Measurements of a 15 nm aluminum film yielded a thermal conductivity of approximately 45 W/(m·K), about 5.3 times below the bulk value. Future directions include local heat transport at grain boundaries and interfaces, directional transport in functional and quantum materials, and measurements at cryogenic temperatures.

Selected publications

Students: Ram Munde, Saumik Dey Shovan, Noah Vaillancourt, Aude Johanna Walther.

Closed-loop thermal-aware heterogeneous integration connecting nanoscale thermal metrology, functional thermal materials, and thermal-aware co-design

Thermal measurements guide material growth and thermal-aware device co-design. View full-size figure. Quantitative probe calibration and thermal maps are reported in Munde et al., Journal of Applied Physics (2026).

Other Research Projects

  1. Nuclear Scintillator Materials

    We study the growth and characterization of nuclear scintillator materials, which convert ionizing radiation into detectable light. The project examines how material quality influences radiation detection and scintillation response. This work is funded by the U.S. Nuclear Regulatory Commission (NRC).

    Students: Noah Vaillancourt.

  2. CMOS+X Chip Tapeout and Device Integration

    Through the Northwest AI Hub CMOS+X Route (CXR) program, we integrate emerging devices with commercial complementary metal-oxide-semiconductor (CMOS) circuits. We completed a 40 nm chip tapeout in the first CXR run and are now testing the chip and integrating the X devices to evaluate their behavior within the system. For the second CXR run at 28 nm, our design is in progress, with agentic artificial intelligence (AI) assisting the design workflow.

    Students: Heng-Ray Chuang, Yifan Wang, Hyeonjun Bae.

  3. Exploratory Project: Agentic AI Platform for Chip Design

    We are exploring an agentic AI platform to assist chip design by connecting design tools, device models, and simulation workflows. The platform is being used to enhance our ongoing 28 nm CXR design cycle. The broader goal is to help researchers evaluate candidate circuits and integration choices more efficiently.

    Students: Meera Srinivas.