Spin based Information Processing and Storage
Valley-coupled-Spintronics
We proposed valley-coupled spintronic devices based on monolayer WSe2 that utilize Valley-Spin Hall (VSH) effect to switch nano-magnets. The unique features of the proposed device are (a) the ability to switch magnets with perpendicular magnetic anisotropy (PMA) and (b) an integrated gate that can modulate the charge/spin current flow. The former attribute results in high energy efficiency (compared to the Giant-Spin Hall (GSH) effect based devices with in-plane MA (IMA) magnets). The latter feature averts the need for additional access transistor in a memory array leading to high integration density.
VSH effect in 2D Transition-Metal Dichalcogenide (TMD) based Non-volatile Memories
Spin-based storage has emerged as a promising alternative to standard charge-based memories due to zero array stand-by leakage, non –volatility and high integration density. However, low write efficiency and self-conflicting design requirements for read and write make it challenging to design low power robust spin-memories. At ICDL, we are exploring novel techniques at the device, circuit and array level to counter the issues associated with spin-based storage. This includes the device-circuit-array co-design for memories employing voltage based magnetization switching phenomena, development of variation-tolerant design methodologies for memories with separate read-write paths and techniques to enhance the magneto resistance. We are also exploring spin-based logic based on multi-terminal spin devices.
The quest for a universal memory which offers high speed, energy efficiency, stability, endurance, distinguishability, integration density and non-volatility still continues, as several of the existing candidates, though promising, suffer from one or the other design issues. As one of the solutions, we explored 2D TMD spin-based memory design, which offers many other intriguing possibilities for various flavors of non-volatile memory design, such as lower write time and switching/write power even with higher integration density compared to standard CMOS. We proposed two flavours of VSH magnetic RAMs namely: (a) Single ended VSH-MRAM and (b) Differential DVSH-MRAM. The proposed memory designs showcased high integration density align with ultra low power memory operations compared to the traditional GSH-MRAMs.
VSH effect based Non-volatile Memories and Flip-Flops with Electrical-Isolation of Read and Write (EIRW) Paths
Proposed (D)VSH-MRAMs exhibit 1) access transistor less compact layout due to an integrated back-gate, and 2) field-free PMA-based device design supported by the generated spin currents with out-of-plane spins, leading to reduction in write power. However, large series resistance (RS) in 2D TMD channel, along which write and read currents flow, may compromise the benefits of VSH-MRAMs. To mitigate the issue, we also design another flavor of VSH effect-based devices that not only maintain the perks of VSH-MRAMs but also attain lower RS by electrically isolating read and write paths (EIRW). This is achieved by designing electrically-isolated but magnetically-coupled PMA magnets (FLW and FLR) via interlayer exchange-coupling.
We explore circuit designs to maximize the benefits of the proposed devices (EIRW-VSH devices) in non-volatile memories and flip-flops. For memories, we obtain improvement in read performance such as 39%-42% and 36%-46% reduction in read time and energy, respectively, and 1.1X-1.3X larger sense margin, compared to VSH-MRAMs. For non-volatile flip-flops, we achieve 74~75% and 55~59% lower backup and restore energies compared to the existing spin-based designs.
References:
[2] K. Cho et al., “Utilizing Valley-Spin Hall Effect in WSe2 for Low Power Non-Volatile Flip-Flop Design,” Device Research Conference, 2020.
[3] K. Cho et al., “Utilizing Valley–Spin Hall Effect in Monolayer WSe2 for Designing Low Power Nonvolatile Spintronic Devices and Flip-Flops,” IEEE Transactions on Electron Devices, 2021.