Publications

Journals:

2019

S. K. Thirumala and S. K. Gupta "Reconfigurable Ferroelectric Transistor- Part II: Application in Low-Power Nonvolatile Memories", IEEE Transactions on Electronic Devices (TED), 2019.
N. Thakuria, A. K. Saha, S. K. Thirumala, B. Jung and S. K. Gupta, "Oscillators Utilizing Ferroelectric Based Transistors and their Coupled Dynamics", IEEE Transactions on Electronic Devices (TED), 2019.
S. K. Thirumala and S. K. Gupta "Reconfigurable Ferroelectric Transistor- Part I: Device Design and Operation", IEEE Transactions on Electronic Devices (TED), 2019.
Zhesheng Shen, Srivatsa Srinivasa, Ahmedullah Aziz, Suman Datta, Vijaykrishnan Narayanan, Sumeet Kumar Gupta, "SRAMs and DRAMs with separate Read-Write Ports Augmented by Phase Transition Materials", IEEE Transactions on Electronic Devices (TED), 2019.

2018

Ahmedullah Aziz, Sumeet Kumar Gupta, "Threshold Switch Augmented STT MRAM: Design Space Analysis and Device-Circuit Co-Design" IEEE Transactions on Electronic Devices (TED), 2018.
Yuhua Liang, Xueqing Li, Sumitha George, Srivatsa Srinivasa, Zhangming Zhu, Sumeet Kumar Gupta, Suman Datta, Vijaykrishnan Narayanan, "Influence of Body Effect on Sample and Hold Circuit Design using Negative Capacitance FET", IEEE Transactions on Electronic Devices (TED), 2018.
X. Li, S. George, Y. Liang, K. Ma, A. Aziz, S. K. Gupta, J. Sampson, M-F. Chang, Y. Liu, H. Yang, S. Datta and V. Narayanan, "Lowering Area Overheads of FeFET-Based Energy-Efficient Nonvolatile Flip-Flops", IEEE Transactions on Electronic Devices (TED), 2018.
S. George, X. Li, M. J. Liao, K. Ma, S. Srinivasa, K. Mohan, A. Aziz, J. Sampson, S. K. Gupta and V. Narayanan, "Symmetric 2-D-Memory Access to Multidimensional Data", IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 2018.
S. Srinivasa, X. Li, M. Chang, J. Sampson, S. K. Gupta and V. Narayanan, "Compact 3-D-SRAM Memory With Concurrent Row and Column Data Access Capability Using Sequential Monolithic 3-D Integration", IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 2018.
A. K. Saha, S. Datta, S. K. Gupta, "“Negative capacitance” in resistor-ferroelectric and ferroelectric-dielectric networks: Apparent or intrinsic?", Journal of Applied Physics (JAP), 2018.

2017

S. Gupta, M. Steiner, A. Aziz, V. Narayanan, S. Datta and S. K. Gupta, "Device-circuit analysis of ferroelectric FETs for low-power logic", IEEE Transactions on Electron Devices (TED), 2017.
X. Li, J. Sampson, A. Khan, K. Ma, S. George, A. Aziz, S. K. Gupta, S. Salahuddin, M. Chang, S. Datta and V. Narayanan, "Enabling energy-efficient nonvolatile computing with negative capacitance FET", IEEE Transactions on Electron Devices (TED), 2017.
X. Li, K. Ma, S. George, W. Khwa, J. Sampson, S. K. Gupta, Y. Liu, M. Chang, S. Datta and V. Narayanan, "Design of nonvolatile SRAM with ferroelectric FETs for energy-efficient backup and restore", IEEE Transactions on Electron Devices (TED), 2017.
A. Aziz, N. Shukla, S. Datta and S. K. Gupta, "Steep switching hybrid phase transition FETs (hyper-FET) for low power applications: A device-circuit co-design perspective—Part II", IEEE Transactions on Electron Devices (TED), 2017.
A. Aziz, N. Shukla, S. Datta and S. K. Gupta, "Steep switching hybrid phase transition FETs (hyper-FET) for low power applications: A device-circuit co-design perspective—Part I", IEEE Transactions on Electron Devices (TED), 2017.

2016

A. Aziz, N. Jao, S. Datta and S. K. Gupta, "Analysis of functional oxide based selectors for cross-point memories", IEEE Transactions on Circuits and System I (TCAS): Regular Papers, 2016.
S. Srinivasa, A. Aziz, N. Shukla, X. Li, J. Sampson, S. Datta, J. P. Kulkarni, V. Narayanan and S. K. Gupta, "Correlated material enhanced SRAMs with robust low power operation", IEEE Transactions on Electron Devices (TED), 2016.
M. S. Kim, W. C. Wissing, X. Li, J. Sampson, S. Datta, S. K. Gupta and V. Narayanan, "Comparative area and parasitics analysis in FinFET and heterojunction vertical TFET standard cells", ACM Journal on Emerging Technologies in Computing Systems (JETC), 2016.
A. Aziz, S. Ghosh, S. Datta and S. K. Gupta, "Physics-based circuit-compatible SPICE model for ferroelectric transistors", IEEE Electron Device Letters (EDL), 2016.
M. S. Kim, W C- Wissing*, X. Li, J. Sampson, S. Datta, S. K. Gupta and V. Narayanan, “Comparative Area and Parasitics Analysis in FinFET and Hetero-junction Vertical TFET Standard Cells”, ACM Journal of Emerging Technologies in Computing, vol. 12, no. 4, July 2016, pp: 38.1-38:23.

2015

N. Shukla, A. V. Thathachary, A. Agrawal, H. Paik, A. Aziz, D. G. Schlom, S. K. Gupta, R. E. Herbert and S. Datta "A steep-slope transistor based on abrupt electronic phase transition", Nature communications, 2015

Pre-2014

W. S. Cho, S. K. Gupta and K. Roy, “Device-Circuit Analysis of Double-Gate MOSFETs and Schottky-Barrier FETs: A Comparison Study for Sub-10nm Technologies”, IEEE Transactions on Electron Devices, vol. 61, no. 12, Dec 2014.
S. H. Choday, S. K. Gupta and K. Roy, “Write-Optimized STT-MRAM Bit-cells Using Asymmetrically Doped Transistors”, IEEE Electron Device Letters, vol. 35, no. 11, Nov 2014.
S. K. Gupta and K. Roy, “Device-Circuit Co-optimization for Robust Design of FinFET-based SRAMs ”, IEEE Design & Test of Computers, vol. 30, no. 6, Dec. 2013 (Invited).
S. K. Gupta, J. P Kulkarni and K. Roy, “Tri-Mode Independent Gate FinFET-based SRAM with Pass-Gate Feedback: A Device-Circuit Co-design Approach for Enhanced Cell Stability”, IEEE Transactions on Electron Devices, vol. 60, no. 11, Nov. 2013.
N. N. Mojumder, X. Fong, C. Augustine, S. K. Gupta, S. H. Choday and K. Roy, “Spin-Transfer Torque MRAMs for Low Power Applications”, ACM Journal of Emerging Technologies in Computing, vol. 9, no. 2, Sept. 2013.
S. K. Gupta, J. P Kulkarni, S. Datta and K. Roy, “Heterojunction Intra-band Tunneling (HIBT) FETs for Low Voltage SRAMs”, IEEE Transactions on Electron Devices, vol. 59, no.12, Dec. 2012.
S. K. Gupta, G. Panagopoulos and K. Roy, “NBTI in n-type SOI access FinFETs in 6T SRAM and its impact on cell stability and performance", IEEE Transactions on Electron Devices, vol. 59, no. 10, Oct. 2012.
M. Sharad, S. K. Gupta, S. Raghunathan, P. Irazoqui and K. Roy, " Low-Power Architecture for Epileptic Seizure Detection Based on Reduced Complexity DWT", ACM Journal on Emerging Technologies in Computing Systems, vol. 8, no. 2, June 2012.
F. Moradi, S. K. Gupta, G. Panagopoulos, H. Mahmoodi, D. T. Wisland and K. Roy, “Asymmetrically-doped (AD) FinFET for Low Power Robust SRAMs”, IEEE Transactions on Electron Devices, vol. 58, no. 12, December 2011.
S. K. Gupta, S. P. Park and K. Roy, “Tri-mode Independent Gate FinFETs for Dynamic Voltage/Frequency Scalable 6T SRAMs”, IEEE Transactions on Electron Devices, vol. 58, no. 11, November 2011.
S. Raghunathan, S. K. Gupta, H. Markandeya, P.P. Irazoqui and K. Roy, “Ultra-LowPower Algorithm design for Implantable Devices- Application to Epilepsy Prostheses”, Journal of Low Power Electronics and Applications, vol. 1, no. 1, May 2011 (Invited).
N. N. Mojumder, S. K. Gupta, S. H. Choday, D. E. Nikonov and K. Roy, “ThreeTerminal Dual-Pillar STT-MRAM Device for High-Performance Robust Memory Applications," IEEE Transactions on Electron Devices, vol. 58, no. 5, May 2011.
A. Goel, S. K. Gupta and K. Roy, “Asymmetric Drain Spacer Extension (ADSE) FinFETs for Low Power and Robust SRAMs”, IEEE Transactions on Electron Devices, vol. 58, no. 2, Feb 2011.
S. Raghunathan, S. K. Gupta, H. Markandeya, K. Roy and P. P. Irazoqui, “A hardware-algorithm co-design approach to optimize seizure detection algorithms for implantable applications”, Journal of Neuroscience Methods, vol 193, no. 1, Oct. 2010.
S. K. Gupta, A. Raychowdhury and K. Roy, "Digital computation in sub-threshold regime for ultra-low power operation: A device-circuit-architecture co-design perspective”, Proceedings of the IEEE, vol. 98, no. 2, Feb 2010 (Invited).
S. Raghunathan, S. K. Gupta, M. P. Ward, R. M Worth, K. Roy and P. Irazoqui, “The design and hardware implementation of a low-power real-time seizure detection algorithm”, Journal of Neural Engineering, vol. 6, 056005, Oct. 2009.
S. K. Gupta, A. Raychowdhury and K. Roy, “Compact models considering incomplete voltage swing in CMOS circuits at ultra-low voltages: A circuit perspective on limits of switching energy”, Journal of Applied Physics, vol. 105, no. 9, 094901, May 2009.
M. J. Kumar, V. Venkataraman and S. K. Gupta, "A New Grounded Lamination Gate (GLG) for Diminished Fringe Capacitance Effects in High-K Gate Dielectric MOSFETs", IEEE Transactions on Electron Devices, vol. 53, no. 10, October 2006.
M. J. Kumar, S. K. Gupta and V. Venkataraman, “Compact Modeling of the Effects of Parasitic Internal Fringe Capacitance on the Threshold Voltage of High-K Gate Dielectric Nanoscale SOI MOSFETs”, IEEE Transactions on Electron Devices, vol. 53, no. 4, April 2006.
V. Venkataraman, S. K. Gupta and M. J. Kumar, "On the Parasitic Gate Capacitance of Small Geometry MOSFETs," IEEE Transactions on Electron Devices, vol. 52, no. 7, July 2005.