Conference Proceedings

2021

A. K. Saha, and S. K. Gupta, “Effective Ferroelectric Permittivity in Metal-Ferroelectric-Insulator-Semiconductor (MFIS) Heterostructures: The Implications of Hard and Soft Domain Walls”, Material Research Society (MRS) Meeting, 2021 (Invited)
A. K. Saha and S. K. Gupta, “Multi-Domain Ferroelectric FETs with Negative and Enhanced Positive Capacitance for Logic Applications”, IEEE International Conference on Simulation of Semiconductor Processes and Devices (SISPAD), 2021 (Invited)
S. Alam, N. Amin, S. K. Gupta, and A. Aziz, “Monte Carlo Variation Analysis of NCFET-based 6-T SRAM: Design Opportunities and Trade-offs”, Great Lakes Symposium on VLSI (GLSVLSI) 2021 (Invited)
W. Chakraborty, M. S. Jose, J. Gomez, A. K. SahaG, K. A. Aabrar, P. Fay, S. K .Gupta, and S. Datta, “Higher-k Zirconium Doped Hafnium Oxide (HZO) Trigate Transistors with Higher DC and RF Performance and Improved Reliability”, VLSI Technology Symposium, 2021
X. Chen C. L. Lo, M. Johnson, Z. Chen, and S. K Gupta, "Modeling and Circuit Analysis of Interconnects with TaS2 Barrier/Liner", Device Research Conference (DRC), 2021
K. Cho, X. Fong, S. K. Gupta, "Exchange-Coupling-Enabled Electrical-Isolation of Compute and Programming Paths in Valley-Spin Hall Effect based Spintronic Device for Neuromorphic Applications", Device Research Conference (DRC), 2021

2020

A. K. Saha, M. Si, K. Ni, S. Datta, P. D. Ye, and S. K. Gupta, “Ferroelectric Thickness Dependent Domain Interactions in FEFETs for Memory and Logic: A Phase-field Model based Analysis”, International Electron Device Meetings (IEDM), 2020
S. K. Thirumala, A. Raha, V. Raghunathan and S. K. Gupta, “IPS-CiM: Enhancing Energy Efficiency of Intermittently Powered Systems with Compute-in-Memory”, International Conference on Computer Design (ICCD), 2020
K. Cho, S. K. Thirumala, X. Liu, N. Thakuria, Z. Chen and S. K. Gupta, “Utilizing Valley-Spin Hall Effect in WSe₂ for Low Power Non-Volatile Flip-Flop Design,” Device Research Conference (DRC), 2020.
N. Thakuria, A. K. Saha, S. K. Thirumala, D. Schulman, S. Das and S. K. Gupta, “Polarization-induced Strain-coupled TMD FETs (PS FETs) for Non-Volatile Memory Applications,“ Device Research Conference (DRC), 2020
S. K. Thirumala, S. Jain, S. K. Gupta and A. Raghunathan, “Ternary Compute-Enabled Memory using Ferroelectric Transistors for Accelerating Deep Neural Networks,” Design Automation and Test in Europe Conference (DATE), 2020 (Best Paper Nomination)

2019

K. Ni, A. K. Saha, W. Chakraborty, H. Ye, B. Grisafe, J. Smith, G. B. Rayner, S. K. Gupta and S. Datta, “ Equivalent Oxide Thickness (EOT) Scaling With Hafnium Zirconium Oxide High-κ Dielectric Near Morphotropic Phase Boundary”, International Electron Device Meetings (IEDM), 2019
S. K. Thirumala, S. Jain, A. Raghunathan and S.K. Gupta, "Non-Volatile Memory utilizing Reconfigurable Ferroelectric Transistors to enable Differential Read and Energy-Efficient In-Memory Computation", Proceedings of the International Symposium on Low Power Electronics and Design (ISLPED), 2019.
S. K. Thirumala, A. Raha, V. Narayanan, V. Raghunathan and S. K. Gupta, "Non-volatile Logic and Memory based on Reconfigurable Ferroelectric Transistors", 15th IEEE/ACM International Symposium on Nanoscale Architectures (NANOARCH), 2019. (Best Paper Award)
S. K. Thirumala, T. Hung, A. Raha, N. Thakuria, K. Cho, V. Raghunathan, Z. Chen and S. K. Gupta "WSe2 based Valley-Coupled-Spintronic Devices for Low Power Non-Volatile Memories", 77th Device Research Conference (DRC), 2019.
S. Dutta, A. K. Saha, P. Panda, W. Chakraborty, J. Gomez, A. Khanna, S. Gupta, K. Roy, S. Datta, "Biologically Plausible Ferroelectric Quasi-Leaky Integrate and Fire Neuron", Symposium on VLSI Technology, 2019.
A. K Saha, B. Grisafe, S. Datta and S. K Gupta, "Microscopic Crystal Phase Inspired Modeling of Zr Concentration Effects in Hf1-xZrxO2 Thin Films", Symposium on VLSI Technology, 2019.

2018

S. Srinivasa, A. K. Ramanathan, X. Li, W. Chen, F. Hsueh, C. Yang, C. Shen, J. Shieh, S. K. Gupta, M. M. Chang, S. Ghosh, J. Sampson and V. Narayanan, "A Monolithic-3D SRAM Design with Enhanced Robustness and In-Memory Computation Support", Proceedings of the International Symposium on Low Power Electronics and Design (ISLPED), 2018.
S. K. Thirumala, A. Raha, H. Jayakumar, K. Ma, V. Narayanan, V. Raghunathan and S. K. Gupta "Dual Mode Ferroelectric Transistor based Non-Volatile Flip-Flops for Intermittently-Powered Systems", Proceedings of the International Symposium on Low Power Electronics and Design (ISLPED), 2018. (Best Paper Nominee)
A. K Saha and S. K Gupta, "Modeling and Comparative Analysis of Hysteretic Ferroelectric and Anti-ferroelectric FETs", 76th Device Research Conference (DRC), 2018.
M. Jerry, J. A. Smith, K. Ni, A. Saha, S. K. Gupta and Suman Datta "Insights on the DC Characterization of Ferroelectric Field-Effect-Transistors", 76th Device Research Conference (DRC), 2018.
N. Thakuria, D. Schulmarr, S. Das and S. K. Gupta, "2-Transistor Schmitt Trigger based on 2D Electrostrictive Field Effect Transistors", 76th Device Research Conference (DRC), 2018
A. Aziz, N. Shukla, A. Seabaugh, S. Datta and S. K. Gupta "Cockcroft-Walton Multiplier based on Unipolar Threshold Switch", 76th Device Research Conference (DRC), 2018
A. Aziz, R. E. Herbert, S. K. Gupta and N. Shukla "A Three-Terminal Edge-Triggered Mott Switch", 76th Device Research Conference (DRC), 2018
S. K. Thirumala and S. K. Gupta, "Gate Leakage in Non-Volatile Ferroelectric Transistors: Device-Circuit Implications", 76th Device Research Conference (DRC), 2018
Y. Huang, M. Chiang, S. Wang and Sumeet Kumar Gupta "An area efficient low-voltage 6-T SRAM cell using stacked silicon nanowires" International Conference on IC Design & Technology (ICICDT), 2018.
A. De, A. Iyengar, M. N. I. Khan, S-H. Lin, S. Thirumala, S. Ghosh and S. K. Gupta, "CTCG: Charge-Trap Based Camouflaged Gates for Reverse Engineering Prevention", IEEE International Symposium on Hardware Oriented Security and Trust (HOST), 2018.
A. Aziz, E. T. Breyer, A. Chen, X. Chen, S. Datta, S. K. Gupta, M. Hoffmann, X. S. Hu, A. Ionescu, M. Jerry, T. Mikolajick, H. Mulaosmanovic, K. Ni, M. Niemier, I. O'Connor, A. Saha, S. Slesazeck, S. K. Thirumala and X. Yin, "Computing with ferroelectric FETs: Devices, models, systems, and applications" Design, Automation & Test in Europe Conference & Exhibition (DATE), 2018.

2017

A. K. Saha, P. Sharma, I. Dabo, S. Datta and S. K. Gupta, "Ferroelectric transistor model based on self-consistent solution of 2D Poisson's, non-equilibrium Green's function and multi-domain Landau Khalatnikov equations", IEEE International Electron Devices Meeting (IEDM), 2017.
A. Aziz and S. K. Gupta, "Read-Enhanced Spin Memories Augmented by Phase Transition Materials", 60th IEEE International Midwest Symposium on Circuits and Systems (MWSCAS), 2017.
A. Aziz, N. Jao, S. Datta, V. Narayanan and S. K. Gupta, "A computationally efficient compact model for leakage in cross-point array", International Conference on Simulation of Semiconductor Processes and Devices (SISPAD), 2017.
S. R. Srinivasa, K. Mohan, W. Chen, K. Hsu, X. Li, M. Chang, S. K. Gupta, J. Sampson and V. Narayanan, "Improving FPGA design with monolithic 3D integration using high dense inter-stack via", IEEE Computer Society Annual Symposium on VLSI (ISVLSI), 2017.
P. Sharma, J. Zhang, A. K. Saha, S. K. Gupta and S. Datta, "Negative capacitance transients in metal-ferroelectric Hf0.5Zr0.5O2-Insulator-Semiconductor (MFIS) capacitors", 75th Device Research Conference (DRC), 2017.
A. Aziz, X. Li, N. Shukla, S. Datta, M. Chang, V. Narayanan and S. K. Gupta, "Low power current sense amplifier based on phase transition material", 75th Device Research Conference (DRC), 2017.
S. Datta, A. Seabaugh, M. Niemier, A. Raychowdhury, D. Schlom, D. Jena, G. Xing, H-S P. Wong, E. Pop, S. Salahuddin, S. K. Gupta and S. Guha, "In quest of the next information processing substrate", 54th ACM/EDAC/IEEE Design Automation Conference (DAC), 2017.
P. Sharma, K. Tapily, A. K. Saha, J. Zhang, A. Shaughnessy, A. Aziz, G. L. Snider, S. K. Gupta, R. D. Clark and S Datta, "Impact of total and partial dipole switching on the switching slope of gate-last negative capacitance FETs with ferroelectric hafnium zirconium oxide gate stack", Symposium on VLSI Technology, 2017.
S. K. Gupta, D. Wang, S. George, A. Aziz, X. Li, S. Datta, and V. Narayanan, "Harnessing ferroelectrics for non-volatile memories and logic", 18th International Symposium on Quality Electronic Design (ISQED), 2017.

2016

N. Shukla, B. Grisafe, R. K. Ghosh, N. Jao, A. Aziz, J. Frougier, M. Jerry, S. Sonde, S. Rouvimov, T. Orlova, S. K. Gupta and S. Datta, "Ag/HfO2 based threshold switch with extreme non-linearity for unipolar cross-point memory and steep-slope phase-FETs", IEEE International Electron Devices Meeting (IEDM), 2016.
X. Yin, A. Aziz, J. Nahas, S. Datta, S. K. Gupta, M. Niemier and X. S. Hu, "Exploiting ferroelectric FETs for low-power non-volatile logic-in-memory circuits", Proceedings of the 35th International Conference on Computer-Aided Design, 2016.
D. Wang, S. George, A. Aziz, S. Datta, V. Narayanan and S. K. Gupta, "Ferroelectric transistor based non-volatile flip-flop", Proceedings of the International Symposium on Low Power Electronics and Design (ISLPED), 2016.
S. George, A. Aziz, X. Li, M. S. Kim, S. Datta, J. Sampson, S. K. Gupta, V. Narayanan, "Device circuit co design of FEFET based logic for low voltage processors", IEEE Computer Society Annual Symposium on VLSI (ISVLSI), 2016.
A. Aziz, S. Ghosh, S. K. Gupta and S. Datta, "Polarization charge and coercive field dependent performance of negative capacitance FETs", 74th Device Research Conference (DRC), 2016.
J. Frougier, N. Shukla, D. Deng, M. Jerry, A. Aziz, L. Liu, G. Lavallee, T. S. Mayer, S. K. Gupta and S. Datta, "Phase-transition-FET exhibiting steep switching slope of 8mV/decade and 36% enhanced ON current", IEEE Symposium on VLSI Technology, 2016.
S. George, K. Ma, A. Aziz, X. Li, A. Khan, S. Salahuddin, M. Chang, S. Datta, J. Sampson, S. K. Gupta and V. Narayanan, "Nonvolatile memory design based on ferroelectric FETs", Proceedings of the 53rd Annual Design Automation Conference, 2016.
S. K. Gupta, A. Aziz, N. Shukla and S. Datta, "On the potential of correlated materials in the design of spin-based cross-point memories", IEEE International Symposium on Circuits and Systems (ISCAS), 2016.
A. Aziz and S. K. Gupta, "Hybrid multiplexing (HYM) for read-and area-optimized MRAMs with separate read-write paths", IEEE Transactions on Nanotechnology, 2016.

2015

A. Aziz, N. Shukla, S. Datta and S. K. Gupta, "Implication of hysteretic selector device on the biasing scheme of a cross-point memory array", International Conference on Simulation of Semiconductor Processes and Devices (SISPAD), 2015.
S. George, A. Aziz, X. Li, J. Sampson, S. Datta, S. K. Gupta and V. Narayanan, "NCFET based logic for energy harvesting systems", SRC TECHCON, 2015.
A. Aziz, N. Shukla, S. Datta and S. K. Gupta, "COAST: Correlated material assisted STT MRAMs for optimized read operation", Proceedings of the International Symposium on Low Power Electronics and Design (ISLPED), 2015.
A. Aziz, W. C. Wissing, M. S. Kim, S. Datta, V. Narayanan and S. K. Gupta, "Single-ended and differential MRAMs based on spin Hall effect: A layout-aware design perspective", IEEE Computer Society Annual Symposium on VLSI (ISVLSI), 2015.
K. Ma, N. Chandramoorthy, X. Li, S. K. Gupta, J. Sampson, Y. Xie and V. Narayanan, "Using Multiple-Input NEMS for Parallel A/D Conversion and Image Processing", IEEE Computer Society Annual Symposium on VLSI (ISVLSI), 2015.
M. S. Kim, W. C. Wissing, J. Sampson, S. Datta, V. Narayanan and S. K. Gupta, "Comparing energy, area, delay tradeoffs in going vertical with CMOS and asymmetric HTFETs", IEEE Computer Society Annual Symposium on VLSI (ISVLSI), 2015.
A. Aziz, N. Shukla, S. Datta and S. K. Gupta, "Read optimized MRAM with separate read-write paths based on concerted operation of magnetic tunnel junction with correlated material", 73rd Annual Device Research Conference (DRC), 2015.
U. Heo, X. Li, H. Liu, S. K. Gupta, S. Datta and V. Narayanan, "A high-efficiency switched-capacitance HTFET charge pump for low-input-voltage applications", 28th International Conference on VLSI Design (VLSID), 2015

Pre 2014

S. Datta, R. Pandey, A. Agrawal, S. K. Gupta and R. Arghavani, “Impact of Contact and Local Interconnect Scaling on Logic Performance”, IEEE Symposium on VLSI Technology 2014. (Invited)
K. Ma, H. Lu, Y. Xiao, Y, Zheng, X. Li, S. K. Gupta, Y. Xie and V. Narayanan, “Independently-Controlled-Gate FinFET 6T SRAM Cell Design for Leakage Current Reduction and Enhanced Read Access Speed”, “IEEE Computer Society Annual Symposium on VLSI (ISVLSI), 2014.
S. K. Gupta, W. Cho, A, Goud, K, Yogendra and K. Roy, “Design Space Exploration of FinFETs in sub-10nm Technologies for Energy-Efficient Near-Threshold Circuits”, Device Research Conference (DRC), 2013.
A. Goud, S. K. Gupta, S. H. Choday and K. Roy, “Atomistic Tight-Binding based Evaluation of Impact of Gate Underlap on Source to Drain Tunneling in 5 nm Gate Length Si FinFETs“, Device Research Conference (DRC), 2013.
S. K. Gupta and K. Roy, “Spacer Thickness Optimization for FinFET-based Logic and Memories: A Device-Circuit Co-design Approach”, Electro Chemical Society Symposium 2012 (Invited) (Rated amongst the top 8 papers in the conference).
S. K. Gupta, J. P Kulkarni, S. Datta and K. Roy, “Dopant Straggle-Free Heterojunction Intra-band Tunneling (HIBT) FETs with Low Drain-induced Barrier Lowering/Thinning and Reduced Variation in OFF current”, Device Research Conference (DRC), 2012.
D. Lee, S. K. Gupta and K. Roy “High-Performance Low-Energy STT MRAM Based on Balanced Write Scheme”, International Symposium on Low Power Electronics and Design (ISLPED), 2012.
Y. Kim, S. K. Gupta, S. P. Park, G. Panagopoulos and K. Roy “Write-Optimized Reliable Design of STT MRAM” International Symposium on Low Power Electronics and Design (ISLPED), 2012. (Nominated for Best Paper Award).
S. P. Park, S. K. Gupta, N. N. Mojumder, A. Raghunathan and K. Roy, “ Future Cache Design using STT MRAMs for Improved Energy Efficiency: Devices, Circuits and Architecture”, Design Automation Conference (DAC), 2012.
S. K. Gupta, S. P. Park, N. N. Mojumder and K. Roy, “Layout-Aware Optimization of STT MRAMs”, Design Automation and Test in Europe Conference (DATE), 2012.
S. K. Gupta, S. H. Choday and K. Roy, “Exploration of Device-Circuit Interactions in FinFET-based Memories for sub-15nm Technologies using a Mixed Mode Quantum Simulation Framework: Atoms to Systems”, International Electron Device Meetings (IEDM), 2011.
X. Fong, S. K. Gupta, N. N. Mojumder, H. Choday, C. Augustine, and Kaushik Roy, “KNACK: A Hybrid Spin-Charge Mixed-Mode Simulator for Evaluating Different Genres of Spin-Transfer Torque MRAM Bit-cells”, International Conference on Simulation of Semiconductor Processes and Devices (SISPAD), 2011.
N. N. Mojumder, S. K. Gupta and K. Roy, “Dual Pillar Spin Transfer Torque MRAM with tilted magnetic anisotropy for fast and error-free switching and near-disturbfree read operations”, Device Research Conference (DRC), 2011.
S. Dighe, S. K. Gupta, V. De, S. Vangal, N. Borkar, S. Borkar and K. Roy, “A 45nm 48-core IA processor with Variation-Aware Scheduling and Optimal Core Mapping” IEEE Symposium on VLSI Circuits, 2011.
M. Sharad, S. K. Gupta, S. Raghunathan, P. Irazoqui, K. Roy, " Ultra Low Power, LPF-Only DWT Architecture for an Epileptic Seizure Prosthesis Implant", Subthreshold Microelectronics Conference, 2011.
K. Roy, J. P. Kulkarni and S. K. Gupta, “Device/Circuit Interactions at 22nm Technology Node”, Design Automation Conference (DAC), 2009 (Invited).
A. Goel, S. K. Gupta, A. Bansal, M.-H. Chiang and Kaushik Roy, “Double-Gate MOSFETs with Asymmetric Drain Underlap: A device-circuit co-design and optimization perspective for SRAM”, Device Research Conference (DRC), 2009.
S. Raghunathan, S. K. Gupta, H. Markandeya, K. Roy and P. Irazoqui, “Co-design of hardware and software to optimize seizure prediction and detection algorithms towards a closed loop epilepsy prosthesis”, Proceedings of the American Epilepsy Society(AES) Annual Meeting, 2009.
S. Raghunathan, S. K. Gupta, K. Roy and P. Irazoqui, “An implantable ultra-low power digital circuit implementation of a seizure detection algorithm”, BMES Annual Fall Meeting, 2009.
M. J. Kumar, V. Venkataraman and S. K. Gupta, "A New Grounded Lamination Gate (GLG) SOI MOSFET for Diminished Fringe Capacitance Effects," Technical Proceedings of the 2006 NSTI Nanotechnology Conference and Trade Show, pp. 709-712, 2006.
M. J. Kumar, V. Venkataraman and S. K. Gupta, "Compact Modeling of Parasitic Internal Fringe Capacitance and its effect on the Threshold Voltage of High-K Gate Dielectric SOI MOSFETs", Int. Workshop on the Physics of Semiconductor Devices, 2005.