|Event Date:||July 29, 2019|
Abstract: —In this work, we propose a non-volatile memory based on cross-coupled reconfigurable ferroelectric transistors (R-FEFETs) with the features of differential read along with low power computation-in-memory (CiM). Exploiting the recently proposed dynamic modulation of hysteresis in R-FEFETs, we achieve the aforementioned functionalities with just 2 access transistors (in addition to 2 R-FEFETs). The differential access of the proposed memory not only enhances the sense margin during memory reads, but also enables natural computation of AND and NOR logic functions between two bits stored in the array, with the assertion of two word-lines. Using this feature, we propose a CiM architecture involving the use of a compact compute module integrated to a sense amplifier which performs Boolean logic as well as arithmetic operations such as addition (ADD) of two words with a single array access. Unlike existing non-volatile CiM designs, our work features: (i) a self-referenced read operation due to differential access and (ii) a single universal voltage reference for all compute operations. At the array-level, our results show that the proposed design (R-FEFET-CiM) achieves 33%, 27% and 12% lower write, read and compute energies respectively, at iso-access time compared to standard FEFET based CiM design (FEFET-CiM). System analysis performed by integrating our R-FEFET-CiM in the Nios II processor across various benchmarks shows total system energy savings of 24% and 14% compared to near-memory computing and FEFET-CiM, respectively.