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    Project Abstract

    Figure 1: Side view of a vertically integrated 10 GHz evanescent filter with an RFIC embedded inside a silicon interposer along with passive components on the interposer. The filter creates a complete vertical package for the entire circuitry. This design also includes a high efficiency patch antenna top of the package.

    Hybrid circuits have recently been giving way to systems on a chip (SOC) due to improvements in CMOS and SiGe technologies. SOC have been traditionally limited because they cannot incorporate three crucial components of RF systems: high-Q filters and inductors, high value inductors and capacitors, and tunable components.

    This project focuses on tighter integration to address these three limitations. First the expensive RFIC chip (IBM 7RF) is integrated into a less expensive silicon carrier wafer. This brings high value and tunable components to the SOC method. This is followed by vertically integrating this combination of wafers with a high-Q cavity filter. Our group has focused on the high-Q filter and its integration.

    The combination of the IBM 7RF wafer and the silicon carrier wafer has several advantages. First, the passive components normally present on the chip can be pulled off to the carrier. This reduces the size of the chip, while at the same time improving the performance of the passives. Because of the very controlled chip/carrier integration the total package remains planar. This enables us to use thin film connections between the chip and carrier as well as to continue using other wafer processes. Thin film processing allows a greater density of interconnects than wire bonding.

    In order to obtain the desired preselect filtering a high-Q filter is necessary. Traditionaly incorporating an air filled cavity is not feasible due to the increase in size of the system. This size increase is overcome by vertically integrating the chip/carrier combination with a high-Q evanescent cavity filter. One method to reduce the size of this high-Q component is to capactively load the cavites with evanescent posts. This reduces the foot print of the filter itself by more than 70%. The filter is then arranged vertically and integrated directly onto the chip/carrier combination enclosing the wafer components and forming a complete package. Furthermore an antenna can be integrated on top of this package creating a complete RF front end.

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